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Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
Eddie Hung
2020-06-04
1
-1
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+2
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abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
Eddie Hung
2020-05-29
1
-1
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+2
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Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
Eddie Hung
2020-06-03
3
-4
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+4
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tests: fix some test warnings
Eddie Hung
2020-05-25
3
-4
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+4
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printattrs: Add test.
Alberto Gonzalez
2020-05-27
1
-0
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+14
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xaiger: add testcase
Eddie Hung
2020-05-24
1
-0
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+13
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abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
Eddie Hung
2020-05-14
1
-3
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+8
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abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
Eddie Hung
2020-05-14
1
-2
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+21
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abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
Eddie Hung
2020-05-14
1
-5
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+7
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Merge pull request #2028 from zachjs/master
Eddie Hung
2020-05-06
2
-0
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+17
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verilog: allow null gen-if then block
Zachary Snow
2020-05-06
2
-0
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+17
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Merge pull request #2024 from YosysHQ/eddie/primitive_src
Eddie Hung
2020-05-05
1
-0
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+16
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tests: add tests for primitives' src
Eddie Hung
2020-05-04
1
-0
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+16
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verilog: fix specify src attribute
Eddie Hung
2020-05-04
1
-0
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+6
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test: add test for #2014
Eddie Hung
2020-05-02
1
-0
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+12
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Merge pull request #1973 from YosysHQ/eddie/fix1966
Eddie Hung
2020-04-22
1
-1
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+3
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tests: use `yosys-config --datdir` instead of hard-coded
Eddie Hung
2020-04-22
1
-1
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+3
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Merge pull request #1950 from YosysHQ/eddie/design_import
Eddie Hung
2020-04-22
2
-5
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+22
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design: add test
Eddie Hung
2020-04-16
2
-5
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+22
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Merge pull request #1976 from YosysHQ/dave/fix-sim-const
Claire Wolf
2020-04-22
1
-0
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+13
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sim: Fix handling of constant-connected cell inputs at startup
David Shah
2020-04-21
1
-0
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+13
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hierarchy: Convert positional parameters to named.
Marcelina Kościelnicka
2020-04-21
1
-0
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+23
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Merge pull request #1851 from YosysHQ/claire/bitselwrite
Claire Wolf
2020-04-21
13
-0
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+1224
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Remove '-ignore_unknown_cells' option from 'sat'
Eddie Hung
2020-04-20
1
-6
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+6
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Simplify test case script
Eddie Hung
2020-04-20
1
-30
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+17
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Modifications of tests as per Eddie's request
diego
2020-04-20
13
-0
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+1237
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abc9: add testcase reduced from #1970
Eddie Hung
2020-04-20
1
-0
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+19
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tests: add design -delete tests
Eddie Hung
2020-04-16
2
-0
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+18
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ast: Fix handling of identifiers in the global scope
David Shah
2020-04-16
1
-0
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+18
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tests: add testcases from #1876
Eddie Hung
2020-04-14
1
-0
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+60
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tests: add a quick plugin test
Eddie Hung
2020-04-09
3
-0
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+22
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Add support for SystemVerilog-style `define to Verilog frontend
Rupert Swarbrick
2020-03-27
4
-0
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+50
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Add test for abc9+mince issue
David Shah
2020-03-20
1
-0
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+17
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fsm_extract: Initialize celltypes with full design.
Marcin Kościelnicki
2020-03-19
1
-0
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+33
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Add test for `exec` command.
Alberto Gonzalez
2020-03-16
1
-0
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+6
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Merge pull request #1759 from zeldin/constant_with_comment_redux
Miodrag Milanović
2020-03-14
2
-0
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+24
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Add regression tests for new handling of comments in constants
Marcus Comstedt
2020-03-14
2
-0
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+24
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Merge pull request #1754 from boqwxp/precise_locations
Miodrag Milanović
2020-03-14
1
-0
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+8
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verilog: add test
Eddie Hung
2020-03-11
1
-0
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+8
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Added back tests for logger
Miodrag Milanovic
2020-03-13
4
-0
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+24
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Merge pull request #1721 from YosysHQ/dave/tribuf-unused
David Shah
2020-03-10
1
-0
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+14
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deminout: Don't demote inouts with unused bits
David Shah
2020-03-04
1
-0
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+14
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Merge pull request #1718 from boqwxp/precise_locations
Claire Wolf
2020-03-03
1
-2
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+2
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Change attribute search value to specify precise location instead of simple l...
Alberto Gonzalez
2020-02-24
1
-2
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+2
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Merge pull request #1519 from YosysHQ/eddie/submod_po
Claire Wolf
2020-03-03
1
-0
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+124
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Merge branch 'master' into eddie/submod_po
Eddie Hung
2020-02-01
7
-11
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+98
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Add a quick testcase for unknown modules as inout
Eddie Hung
2019-12-09
1
-2
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+24
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Merge pull request #1724 from YosysHQ/eddie/abc9_specify
Eddie Hung
2020-03-02
2
-19
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+1
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Cleanup tests
Eddie Hung
2020-02-27
2
-19
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+1
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ast: fixes #1710; do not generate RTLIL for unreachable ternary
Eddie Hung
2020-02-27
1
-0
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+30
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