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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 12:08:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 722540dbf942d2b8acbaf7372001c7d982eb2845 (patch) | |
| tree | b852f01139a2a9f8b59ffeddfb8edd33a7272557 /tests/various | |
| parent | 5ad3a8528896a2e2539f2de98194eb0a6cce36c9 (diff) | |
| download | yosys-722540dbf942d2b8acbaf7372001c7d982eb2845.tar.gz yosys-722540dbf942d2b8acbaf7372001c7d982eb2845.tar.bz2 yosys-722540dbf942d2b8acbaf7372001c7d982eb2845.zip | |
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/abc9.ys | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 7a3a503e4..9586091c4 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -50,7 +50,7 @@ $_DFF_P_ ff(.C(clk), .D(d), .Q(w)); assign q = w; endmodule EOT -equiv_opt abc9 -lut 4 -dff +equiv_opt -assert abc9 -lut 4 -dff design -load postopt cd abc9_test036 select -assert-count 1 t:$_DFF_P_ @@ -69,8 +69,27 @@ specify endspecify endmodule -module top(input [1:0] i, output o); +module abc9_test037(input [1:0] i, output o); LUT2 #(.mask(4'b0)) lut (.i(i), .o(o)); endmodule EOT abc9 + + +design -reset +read_verilog -icells <<EOT +module abc9_test038(input clk, output w, x, y); +(* init=1'b1 *) wire w; +$_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w)); +(* init=1'bx *) wire x; +$_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x)); +(* init=1'b0 *) wire y; +$_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y)); +endmodule +EOT +simplemap +equiv_opt abc9 -lut 4 -dff +design -load postopt +cd abc9_test038 +select -assert-count 2 t:$_DFF_N_ +select -assert-none c:ff1 c:ff2 %% c:* %D |