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| author | David Shah <dave@ds0.me> | 2020-04-21 08:58:52 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-04-21 08:58:52 +0100 |
| commit | abf81c76396d674833d1dce3f3f75a43f76e2a1f (patch) | |
| tree | 8783842cec0215c2d063ef3647273826d05b0905 /tests/various | |
| parent | c98cde88427aedacbcaf66d915912377ccb0cb01 (diff) | |
| download | yosys-abf81c76396d674833d1dce3f3f75a43f76e2a1f.tar.gz yosys-abf81c76396d674833d1dce3f3f75a43f76e2a1f.tar.bz2 yosys-abf81c76396d674833d1dce3f3f75a43f76e2a1f.zip | |
sim: Fix handling of constant-connected cell inputs at startup
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/sim_const.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys new file mode 100644 index 000000000..d778b92cd --- /dev/null +++ b/tests/various/sim_const.ys @@ -0,0 +1,13 @@ +read_verilog <<EOT + +module top(input clk, output reg [1:0] q); + wire [1:0] x = 2'b10; + always @(posedge clk) + q <= x & 2'b11; +endmodule +EOT + +proc +sim -clock clk -n 1 -w top +select -assert-count 1 a:init=2'b10 top/q %i + |