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author | Eddie Hung <eddie@fpgeh.com> | 2020-05-05 06:49:18 -0700 |
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committer | GitHub <noreply@github.com> | 2020-05-05 06:49:18 -0700 |
commit | 7a62ee57b4953a01637086d409a99b9779a7d6c9 (patch) | |
tree | 65e5a6c22a393ca75421e135bf02e725f45aa9d8 /tests/various | |
parent | 99aff5a0f9f322bf4498fe06094de9919ed56681 (diff) | |
parent | eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37 (diff) | |
download | yosys-7a62ee57b4953a01637086d409a99b9779a7d6c9.tar.gz yosys-7a62ee57b4953a01637086d409a99b9779a7d6c9.tar.bz2 yosys-7a62ee57b4953a01637086d409a99b9779a7d6c9.zip |
Merge pull request #2024 from YosysHQ/eddie/primitive_src
verilog: set src attribute for primitives
Diffstat (limited to 'tests/various')
-rw-r--r-- | tests/various/primitives.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/various/primitives.ys b/tests/various/primitives.ys new file mode 100644 index 000000000..9307ca50f --- /dev/null +++ b/tests/various/primitives.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module top(input a, b, output [5:0] y); +and (y[0], a, b); +nand (y[1], a, b); +or (y[2], a, b); +nor (y[3], a, b); +xor (y[4], a, b); +xnor (y[5], a, b); +endmodule +EOT +select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i +select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i +select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i +select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i +select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i +select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i |