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* simple/peepopt.v tests to various/peepopt.ys with equiv_opt & selectEddie Hung2019-09-051-21/+0
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* Add peepopt_dffmuxext testsEddie Hung2019-09-041-0/+8
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* Use `command -v` rather than `which`Emily2019-09-031-1/+1
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* Add test case for real parametersClifford Wolf2019-08-201-1/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Support explicit FIRRTL properties for better accommodation of ↵Jim Lawson2019-07-311-1/+3
| | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
* Add testEddie Hung2019-06-201-0/+11
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* Add proper test for SV-style arraysClifford Wolf2019-06-201-0/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-191-0/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-0/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-071-1/+2
|\ | | | | | | into tux3-implicit_named_connection
| * SystemVerilog support for implicit named port connectionstux32019-06-061-1/+2
| | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
* | Added tests for attributesMaciej Kurc2019-06-039-0/+219
|/ | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
|\ | | | | Do not use shiftmul peepopt pattern when mul result is truncated
| * Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-281-0/+36
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Add test case from #997Clifford Wolf2019-05-071-0/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-063-0/+32
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| * Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-031-0/+9
| |\ | | | | | | Improve pmgen, Add "peepopt" pass with shift-mul pattern
| | * Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-301-0/+9
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-031-0/+22
| |\ \ | | | | | | | | Fix width detection of memory access with bit slice
| | * | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+22
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * / Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-011-0/+1
| |/ | | | | | | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting).
* / Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add retime testEddie Hung2019-04-051-0/+6
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* fix local name resolution in prefix constructsZachary Snow2019-03-181-0/+56
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* Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-0/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-0/+1
| | | | Mark dff_init.v as expected to fail since it uses "initial value".
* Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-1/+0
| | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
* Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-171-0/+26
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| * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
* | Extend testcaseEddie Hung2019-02-061-2/+34
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* | Add testcaseEddie Hung2019-02-061-0/+10
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* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-181-90/+0
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* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+17
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* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+76
| | | | This time doing the changes mostly in AST before RTLIL generation
* Fix tests/simple/specify.vClifford Wolf2018-03-271-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-0/+31
| | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-291-32/+0
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* $size() now works correctly for all cases!Udi Finkelstein2017-09-261-5/+11
| | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
* $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-261-8/+18
| | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
* Added $bits() for memories as well.Udi Finkelstein2017-09-261-6/+5
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* $size() now works with memories as well!Udi Finkelstein2017-09-261-2/+4
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* Add $size() function. At the moment it works only on expressions, not on ↵Udi Finkelstein2017-09-261-0/+15
| | | | memories.
* Squelch trailing whitespaceLarry Doolittle2017-04-121-1/+1
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* Fixed typo in tests/simple/arraycells.vClifford Wolf2017-01-041-1/+1
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* Added support for hierarchical defparamsClifford Wolf2016-11-151-0/+23
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* Add optional SEED=n command line option to Makefile, and -S n command line ↵Eric Smith2016-09-221-1/+12
| | | | option to test scripts, for deterministic regression tests.
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