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* Fix valgrind tests when using verificMiodrag Milanovic2022-03-304-8/+8
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* fix iverilog compatibility for new case expr testsZachary Snow2022-01-032-2/+2
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* sv: fix size cast clipping expression widthZachary Snow2022-01-031-0/+7
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* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-0/+43
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-252-0/+42
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Fix "make vgtest" so it runs to the end (but now it fails ;)Claire Xenia Wolf2021-09-2340-79/+79
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-291-0/+273
| | | | | | | | If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen.
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-291-0/+18
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* sv: fix up end label checkingZachary Snow2021-06-161-0/+29
| | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-091-1/+1
|\ | | | | Fixing old e-mail addresses and deadnames
| * More deadname stuffClaire Xenia Wolf2021-06-091-1/+1
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* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-081-0/+11
| | | | | | | | | | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-081-0/+19
|/ | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* verilog: fix case expression sign and width handlingZachary Snow2021-05-252-0/+108
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
* sv: support remaining assignment operatorsZachary Snow2021-05-251-0/+23
| | | | | - Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>= - Unify existing support for: +=, -=, &=, |=, ^=
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-0/+15
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-0/+29
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* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-012-0/+109
| | | | | - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else
* Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-112-0/+94
|\ | | | | verilog: refactored constant function evaluation
| * verilog: refactored constant function evaluationZachary Snow2021-02-042-0/+94
| | | | | | | | | | | | | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-0/+10
|/ | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-0412-0/+312
|\ | | | | verilog: significant block scoping improvements
| * verilog: significant block scoping improvementsZachary Snow2021-01-3112-0/+312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | Merge pull request #2436 from dalance/fix_generatewhitequark2021-02-032-7/+4
|\ \ | | | | | | Fix begin/end in generate
| * | Fix begin/end in generatedalance2020-11-112-7/+4
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* | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-0/+20
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* | verilog: allow spaces in macro argumentsZachary Snow2021-01-201-0/+28
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* tests/simple: remove "nullglob" shoptXiretza2020-09-211-1/+0
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* Module name scope supportZachary Snow2020-08-201-0/+16
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* Merge pull request #2339 from zachjs/display-format-0sclairexen2020-08-181-0/+7
|\ | | | | Allow %0s $display format specifier
| * Allow %0s $display format specifierZachary Snow2020-08-091-0/+7
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* | Merge pull request #2338 from zachjs/const-branch-finishclairexen2020-08-181-0/+39
|\ \ | | | | | | Propagate const_fold through generate blocks and branches
| * | Propagate const_fold through generate blocks and branchesZachary Snow2020-08-091-0/+39
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* / Fix generate scoping issuesZachary Snow2020-07-311-0/+85
|/ | | | | | | | | - expand_genblock defers prefixing of items within named sub-blocks - Allow partially-qualified references to local scopes - Handle shadowing within generate blocks - Resolve generate scope references within tasks and functions - Apply generate scoping to genvars - Resolves #2214, resolves #1456
* Expand tests/simple/constmuldivmod.vXiretza2020-05-281-1/+41
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* Bugfix in partsel.v signed indices test casesClaire Wolf2020-05-021-2/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add tests based on the test case from #1990Claire Wolf2020-05-021-0/+46
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add dynamic slicing Verilog testcaseEddie Hung2020-03-311-0/+12
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* Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-0/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Make SV2017 compliant courtesy of @wsnyderEddie Hung2019-12-121-3/+1
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* simple/peepopt.v tests to various/peepopt.ys with equiv_opt & selectEddie Hung2019-09-051-21/+0
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* Add peepopt_dffmuxext testsEddie Hung2019-09-041-0/+8
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* Use `command -v` rather than `which`Emily2019-09-031-1/+1
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* Add test case for real parametersClifford Wolf2019-08-201-1/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Support explicit FIRRTL properties for better accommodation of ↵Jim Lawson2019-07-311-1/+3
| | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
* Add testEddie Hung2019-06-201-0/+11
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* Add proper test for SV-style arraysClifford Wolf2019-06-201-0/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-191-0/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-0/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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