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| author | Zachary Snow <zach@zachjs.com> | 2021-07-29 12:35:22 -0400 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-07-29 20:55:31 -0400 |
| commit | 4fec3a85cd7d0fcd35f958bfc89090df25f7de3c (patch) | |
| tree | e78acff59083ecd64fac829b0d3d33548f76329e /tests/simple | |
| parent | 87ef1dd80536d65fde3833c7a504c9b5de5c3ea9 (diff) | |
| download | yosys-4fec3a85cd7d0fcd35f958bfc89090df25f7de3c.tar.gz yosys-4fec3a85cd7d0fcd35f958bfc89090df25f7de3c.tar.bz2 yosys-4fec3a85cd7d0fcd35f958bfc89090df25f7de3c.zip | |
genrtlil: add width detection for AST_PREFIX nodes
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/loop_prefix_case.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/simple/loop_prefix_case.v b/tests/simple/loop_prefix_case.v new file mode 100644 index 000000000..7ee28ed70 --- /dev/null +++ b/tests/simple/loop_prefix_case.v @@ -0,0 +1,18 @@ +module top( + input wire x, + output reg y +); + localparam I = 1; + genvar i; + generate + for (i = 0; i < 1; i = i + 1) begin : blk + wire [i:i] z = x; + end + endgenerate + always @* begin + case (blk[I - 1].z) + 1: y = 0; + 0: y = 1; + endcase + end +endmodule |