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| author | Zachary Snow <zach@zachjs.com> | 2021-01-28 11:26:21 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-01-28 11:26:35 -0500 |
| commit | 27257a419fe94e10f24eea916c56821e22e43cc5 (patch) | |
| tree | e4f30ff6b441acbe2e07a2cc1785a2743081866d /tests/simple | |
| parent | 98afe2b7589181c39281a6c58540f6756395e1d9 (diff) | |
| download | yosys-27257a419fe94e10f24eea916c56821e22e43cc5.tar.gz yosys-27257a419fe94e10f24eea916c56821e22e43cc5.tar.bz2 yosys-27257a419fe94e10f24eea916c56821e22e43cc5.zip | |
verilog: strip leading and trailing spaces in macro args
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/macro_arg_surrounding_spaces.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v new file mode 100644 index 000000000..3dbb5ea01 --- /dev/null +++ b/tests/simple/macro_arg_surrounding_spaces.v @@ -0,0 +1,20 @@ +module top( + IDENT_V_, + IDENT_W_, + IDENT_X_, + IDENT_Y_, + IDENT_Z_, + IDENT_A_, + IDENT_B_, + IDENT_C_ +); + `define MACRO(dummy, x) IDENT_``x``_ + output wire IDENT_V_; + output wire `MACRO(_,W); + output wire `MACRO(_, X); + output wire `MACRO(_,Y ); + output wire `MACRO(_, Z ); + output wire `MACRO(_, A); + output wire `MACRO(_,B ); + output wire `MACRO(_, C ); +endmodule |