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* Fix for sync_ram_sdp not being final moduleKrystalDelusion2023-02-211-1/+1
| | | | Explicitly declare -top in synth_intel_alm.
* Reenable existing equiv_opt testsJannis Harder2022-10-071-2/+2
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* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-1/+2
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* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-251-6/+4
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add global buffer insertiongatecat2021-05-1513-41/+41
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add IO buffer insertiongatecat2021-05-1513-39/+39
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* tests: Centralize test collection and Makefile generationXiretza2020-09-211-19/+3
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* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-261-3/+40
| | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-2/+3
| | | | | | | | | | | | | | Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-072-11/+11
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* intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-0/+6
| | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-6/+6
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* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-231-6/+4
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* Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-6/+0
| | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-051-0/+6
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* intel_alm: add Cyclone 10 GX testsDan Ravensloft2020-07-0511-2/+236
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* intel_alm: DSP inferenceDan Ravensloft2020-07-051-0/+23
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* synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-041-1/+1
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* Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-1/+2
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* tests: update fsm.ys resource countEddie Hung2020-07-041-4/+4
| | | | | Suspect it is to do with map/set ordering in techmap; should be fixed by #1862?
* intel_alm: fix DFFE matchingDan Ravensloft2020-06-112-4/+4
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* Add missing .gitignore fileClaire Wolf2020-06-041-0/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-0/+20
| | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+12
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* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1510-0/+208
By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
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