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authorJannis Harder <me@jix.one>2022-08-30 13:56:05 +0200
committerJannis Harder <me@jix.one>2022-10-07 16:04:51 +0200
commit0113f44faaa5778afd0fa3afbdbf12f33f2cea4e (patch)
tree24af24f2dfb61ca607b99b5ffee73a54bf6a0fc2 /tests/arch/intel_alm
parent81906aa627ed4a2d232a27a84e050bf86f2f83a6 (diff)
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Reenable existing equiv_opt tests
Diffstat (limited to 'tests/arch/intel_alm')
-rw-r--r--tests/arch/intel_alm/counter.ys4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys
index 56c9cabb3..0a5b9356a 100644
--- a/tests/arch/intel_alm/counter.ys
+++ b/tests/arch/intel_alm/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
+equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
@@ -17,7 +17,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
+equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module