diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-19 13:59:59 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-20 12:44:09 +0200 |
| commit | 50d532f01c3703930240e30c72b726fa66095cf5 (patch) | |
| tree | 94d567468e3015620eb221ac5795c67f4e337bd0 /tests/arch/intel_alm | |
| parent | 93d663be62510b0d062767b288e943f7a9eed9f6 (diff) | |
| download | yosys-50d532f01c3703930240e30c72b726fa66095cf5.tar.gz yosys-50d532f01c3703930240e30c72b726fa66095cf5.tar.bz2 yosys-50d532f01c3703930240e30c72b726fa66095cf5.zip | |
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering. This path was needlessly
overcomplicated and contained bugs.
Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling). This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.
Fixes #2346.
Diffstat (limited to 'tests/arch/intel_alm')
| -rw-r--r-- | tests/arch/intel_alm/mux.ys | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys index 01cc78e1b..ac3b9b08f 100644 --- a/tests/arch/intel_alm/mux.ys +++ b/tests/arch/intel_alm/mux.ys @@ -70,8 +70,9 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT3 -select -assert-count 5 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D +select -assert-max 2 t:MISTRAL_ALUT5 +select -assert-max 5 t:MISTRAL_ALUT6 +select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D design -load read |