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authorDan Ravensloft <dan.ravensloft@gmail.com>2020-07-26 19:11:55 +0100
committerMarcelina Koƛcielnicka <mwk@0x04.net>2020-07-26 23:56:54 +0200
commit62311b7ec0fc92fd78c38dd416551d460f1647a2 (patch)
tree0a3be7860e46a0f17c69b22aed8e2acde3f476d6 /tests/arch/intel_alm
parent9bcde4d82b92c02f0659714d48f3ea01aec3d1cd (diff)
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intel_alm: increase abc9 -W
Diffstat (limited to 'tests/arch/intel_alm')
-rw-r--r--tests/arch/intel_alm/mux.ys12
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys
index 8277e925f..01cc78e1b 100644
--- a/tests/arch/intel_alm/mux.ys
+++ b/tests/arch/intel_alm/mux.ys
@@ -47,9 +47,9 @@ proc
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 3 t:MISTRAL_ALUT5
-select -assert-count 1 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 1 t:MISTRAL_ALUT3
+select -assert-count 2 t:MISTRAL_ALUT6
+select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
design -load read
@@ -69,9 +69,9 @@ proc
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 2 t:MISTRAL_ALUT5
-select -assert-count 4 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 1 t:MISTRAL_ALUT3
+select -assert-count 5 t:MISTRAL_ALUT6
+select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
design -load read