iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	abc9: replace cell type/parameters if derived type already processed (#2991)	Eddie Hung	2021-09-09	1	-0/+7
*	test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.	Marcelina Kościelnicka	2021-08-11	1	-51/+102
*	Add v2 memory cells.	Marcelina Kościelnicka	2021-08-11	1	-17/+17
*	memory_bram: Reuse extract_rdff helper for make_outreg.	Marcelina Kościelnicka	2021-05-25	1	-4/+4
*	Blackbox all whiteboxes after synthesis	gatecat	2021-03-17	1	-9/+9
*	memory_dff: Fix needlessly duplicating enable bits.	Marcelina Kościelnicka	2020-10-22	1	-0/+24
*	tests: Centralize test collection and Makefile generation	Xiretza	2020-09-21	1	-19/+3
*	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	1	-3/+3
*	tests: tidy up testcase	Eddie Hung	2020-06-03	1	-3/+0
*	tests: add ecp5 latch testcase with -abc9	Eddie Hung	2020-05-25	1	-0/+16
*	tests: remove write_ilang	Eddie Hung	2020-04-20	1	-2/+0
*	Merge pull request #1603 from whitequark/ice40-ram_style	whitequark	2020-04-10	1	-0/+330
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\| *	ecp5: do not map FFRAM if explicitly requested otherwise.	whitequark	2020-04-03	1	-16/+62
\| *	ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.	whitequark	2020-02-06	1	-0/+284
* \|	Update bug1630.ys to use -lut 4 instead of lut file	Eddie Hung	2020-02-27	1	-1/+1
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*	Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux	Eddie Hung	2020-02-05	1	-0/+32
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\| *	Add opt_lut_ins pass. (#1673)	Marcelina Kościelnicka	2020-02-03	1	-0/+32
* \|	Update tests with reduced area	Eddie Hung	2020-01-21	1	-3/+3
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*	Add #1630 testcase	Eddie Hung	2020-01-13	2	-0/+2
*	Add testcase from #1459	Eddie Hung	2020-01-06	1	-0/+25
*	Do not do call equiv_opt when no sim model exists	Eddie Hung	2019-12-31	2	-4/+4
*	Call equiv_opt with -multiclock and -assert	Eddie Hung	2019-12-31	1	-1/+1
*	Merge pull request #1599 from YosysHQ/eddie/retry_1588	Eddie Hung	2019-12-30	1	-0/+16
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\| *	Add #1598 testcase	Eddie Hung	2019-12-27	1	-0/+16
* \|	Update resource count	Eddie Hung	2019-12-28	1	-3/+3
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*	Rename memory tests to lutram, add more xilinx tests	Eddie Hung	2019-12-12	1	-3/+3
*	Fixed tests	Miodrag Milanovic	2019-11-11	1	-4/+9
*	Common memory test now shared	Miodrag Milanovic	2019-10-18	2	-22/+1
*	Share common tests	Miodrag Milanovic	2019-10-18	22	-302/+11
*	Fix path to yosys	Miodrag Milanovic	2019-10-18	1	-1/+1
*	Moved all tests in arch sub directory	Miodrag Milanovic	2019-10-18	32	-0/+668