| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | Fix SRL16/32 techmap off-by-one | Eddie Hung | 2019-02-28 | 1 | -18/+24 | |
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| | * | | | | | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 2 | -24/+29 | |
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| | * | | | | | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 2 | -22/+19 | |
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| | * | | | | | | synth_xilinx to now have shregmap call after dff2dffe | Eddie Hung | 2019-02-28 | 1 | -0/+2 | |
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| | * | | | | | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 | |
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| * | | | | | | | Add MUXCY and XORCY to cells_box.v | Eddie Hung | 2019-04-16 | 2 | -0/+15 | |
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| * | | | | | | | Fix spacing | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
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| * | | | | | | | Make cells.box whiteboxes not blackboxes | Eddie Hung | 2019-04-16 | 1 | -2/+2 | |
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| * | | | | | | | read_verilog cells_box.v before techmap | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
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| * | | | | | | | synth_xilinx: before abc read +/xilinx/cells_box.v | Eddie Hung | 2019-04-16 | 1 | -0/+1 | |
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| * | | | | | | | Add +/xilinx/cells_box.v containing models for ABC boxes | Eddie Hung | 2019-04-16 | 2 | -0/+11 | |
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| * | | | | | | | Revert "Add abc_box_id attribute to MUXF7/F8 cells" | Eddie Hung | 2019-04-16 | 1 | -2/+0 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec. | |||||
| * | | | | | | | Add abc_box_id attribute to MUXF7/F8 cells | Eddie Hung | 2019-04-15 | 1 | -0/+2 | |
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| * | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-15 | 3 | -41/+60 | |
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| | * | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-12 | 1 | -1/+9 | |
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| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-12 | 4 | -44/+69 | |
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| | | * | | | | | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 | |
| | | |\ \ \ \ \ | | | | | | | | | | | | | | | | | Add additional cells sim models for core 7-series primitives. | |||||
| | | | * | | | | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | | | * | | | | | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | | | * | | | | | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 | |
| | | | | |_|_|/ | | | |/| | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-04-12 | 1 | -3/+9 | |
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| | * | | | | | | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 | |
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| * | | | | | | Fix cells_map.v some more | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
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| * | | | | | | More fine tuning | Eddie Hung | 2019-04-11 | 1 | -2/+2 | |
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| * | | | | | | Fix cells_map.v | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
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| * | | | | | | Fix typo | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
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| * | | | | | | Juggle opt calls in synth_xilinx | Eddie Hung | 2019-04-11 | 2 | -30/+35 | |
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| * | | | | | | WIP for cells_map.v -- maybe working? | Eddie Hung | 2019-04-10 | 1 | -32/+27 | |
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| * | | | | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 | Eddie Hung | 2019-04-10 | 1 | -31/+38 | |
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| * | | | | | | Fix for when B_SIGNED = 1 | Eddie Hung | 2019-04-10 | 1 | -1/+8 | |
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| * | | | | | | Update doc for synth_xilinx | Eddie Hung | 2019-04-10 | 1 | -7/+8 | |
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| * | | | | | | ff_map.v after abc | Eddie Hung | 2019-04-10 | 1 | -5/+5 | |
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| * | | | | | | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
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| * | | | | | | Move map_cells to before map_luts | Eddie Hung | 2019-04-10 | 1 | -11/+12 | |
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| * | | | | | | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 | |
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| * | | | | | | Update LUT delays | Eddie Hung | 2019-04-10 | 1 | -11/+8 | |
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| * | | | | | | Add cells.lut to techlibs/xilinx/ | Eddie Hung | 2019-04-09 | 2 | -0/+16 | |
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| * | | | | | | synth_xilinx to call abc with -lut +/xilinx/cells.lut | Eddie Hung | 2019-04-09 | 1 | -2/+2 | |
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| * | | | | | | Add delays to cells.box | Eddie Hung | 2019-04-09 | 1 | -4/+12 | |
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| * | | | | | | synth_xilinx with abc9 to use -box | Eddie Hung | 2019-04-09 | 1 | -1/+4 | |
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| * | | | | | | Add techlibs/xilinx/cells.box | Eddie Hung | 2019-04-09 | 2 | -0/+6 | |
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| * | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-09 | 1 | -1/+9 | |
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| * | | | | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 32 | -384/+1646 | |
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| | * | | | | xilinx: Add keep attribute where appropriate | David Shah | 2019-03-22 | 2 | -25/+31 | |
| | | |_|/ | |/| | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 | |
| | | |/ | |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes | Clifford Wolf | 2019-03-12 | 1 | -19/+0 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Fix typo in ice40_braminit help msg | Clifford Wolf | 2019-03-09 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Merge pull request #859 from smunaut/ice40_braminit | Clifford Wolf | 2019-03-09 | 4 | -37/+212 | |
| | |\ \ | | | | | | | | | iCE40 BRAM primitives init from file | |||||
| | | * | | ice40: Run ice40_braminit pass by default | Sylvain Munaut | 2019-03-08 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| | | * | | ice40: Add ice40_braminit pass to allow initialization of BRAM from file | Sylvain Munaut | 2019-03-08 | 3 | -37/+211 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
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index : iCE40/yosys | |
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