iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fix some c++ clang compiler errors	Clifford Wolf	2017-07-03	1	-3/+3
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*	Apply minor coding style changes to coolrunner2 target	Clifford Wolf	2017-07-03	2	-1/+1
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*	Merge pull request #352 from rqou/master	Clifford Wolf	2017-07-03	6	-0/+645
\|\ \| \| \| \|	Initial Coolrunner-II support
\| *	coolrunner2: Add a few more primitives	Robert Ou	2017-06-25	1	-0/+110
\| \| \| \| \| \| \| \|	These cannot be inferred yet, but add them to cells_sim.v for now
\| *	coolrunner2: Initial mapping of latches	Robert Ou	2017-06-25	4	-0/+63
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\| *	coolrunner2: Initial mapping of DFFs	Robert Ou	2017-06-25	4	-0/+76
\| \| \| \| \| \| \| \| \| \|	All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)
\| *	coolrunner2: Remove redundant INVERT_PTC	Robert Ou	2017-06-25	2	-4/+1
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\| *	coolrunner2: Remove debug prints	Robert Ou	2017-06-25	1	-2/+0
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\| *	coolrunner2: Correctly handle $_NOT_ after $sop	Robert Ou	2017-06-25	1	-5/+41
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\| *	coolrunner2: Also construct the XOR cell in the macrocell	Robert Ou	2017-06-25	2	-7/+34
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\| *	coolrunner2: Initial techmapping for $sop	Robert Ou	2017-06-25	4	-153/+268
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\| *	coolrunner2: Initial commit	Robert Ou	2017-06-24	3	-0/+223
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* \|	greenpak4_counters: Changed generation of primitive names so that the ↵	Andrew Zonenberg	2017-06-24	1	-3/+21
\|/ \| \| \|	absorbed register's name is included
*	Add dff2ff.v techmap file	Clifford Wolf	2017-05-31	2	-0/+15
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*	greenpak4_counters: Added support for parallel output from GP_COUNTx cells	Andrew Zonenberg	2017-05-22	1	-17/+70
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*	Add $_ANDNOT_ and $_ORNOT_ gates	Clifford Wolf	2017-05-17	1	-0/+38
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*	Squelch trailing whitespace	Larry Doolittle	2017-04-12	8	-126/+126
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*	Add initial support for both MAX10 and Cyclone IV (E\|GX) FPGAs	dh73	2017-04-05	8	-0/+968
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2017-02-25	1	-3/+4
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\| *	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2017-02-14	1	-2/+0
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\| * \	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2017-02-08	1	-0/+8
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\| * \| \|	greenpak4: Added POUT to GP_COUNTx cells	Andrew Zonenberg	2017-01-01	1	-3/+4
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* \| \| \|	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-0/+16
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* \| \|	Fix double-call of log_pop() in synth_greenpak4	Clifford Wolf	2017-02-14	1	-2/+0
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* \|	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-0/+8
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*	greenpak4: Added INT pin to GP_SPI	Andrew Zonenberg	2016-12-21	1	-1/+3
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*	greenpak4: removed unused MISO pin from GP_SPI	Andrew Zonenberg	2016-12-21	1	-1/+0
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*	greenpak4: Removed SPI_BUFFER parameter	Andrew Zonenberg	2016-12-20	1	-1/+0
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*	greenpak4: replaced MOSI/MISO with single one-way SDAT pin	Andrew Zonenberg	2016-12-20	1	-2/+1
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*	greenpak4: Changed port names on GP_SPI for clarity	Andrew Zonenberg	2016-12-20	1	-4/+4
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*	greenpak4: Initial implementation of GP_SPI cell	Andrew Zonenberg	2016-12-20	1	-0/+27
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*	greenpak4: Updated GP_DCMP cell model	Andrew Zonenberg	2016-12-17	1	-2/+20
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*	greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.	Andrew Zonenberg	2016-12-16	1	-5/+10
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*	greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed ↵	Andrew Zonenberg	2016-12-15	1	-5/+24
\| \| \| \|	interface to GP_DCMPMUX
*	greenpak4: More fixups of GP_DCMPx cells	Andrew Zonenberg	2016-12-15	1	-9/+3
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*	greenpak4: And another typo :(	Andrew Zonenberg	2016-12-15	1	-1/+1
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*	greenpak4: Fixed another typo	Andrew Zonenberg	2016-12-15	1	-1/+1
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*	greenpak4: Fixed typo	Andrew Zonenberg	2016-12-15	1	-1/+1
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*	greenpak4: Cleaned up trailing spaces in cells_sim	Andrew Zonenberg	2016-12-14	1	-60/+60
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*	greenpak4: Added GP_DCMPREF / GP_DCMPMUX	Andrew Zonenberg	2016-12-14	1	-0/+23
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*	Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF	Andrew Zonenberg	2016-12-11	1	-1/+9
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*	greenpak4: Added support for inferred input/output inverters on latches	Andrew Zonenberg	2016-12-10	1	-4/+17
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*	greenpak4: Can now techmap inferred D latches (without set/reset or output ↵	Andrew Zonenberg	2016-12-10	3	-0/+17
\| \| \| \|	inverter)
*	greenpak4: Inverted D latch cells now have nQ instead of Q as output port ↵	Andrew Zonenberg	2016-12-10	1	-15/+15
\| \| \| \|	name for consistency
*	Added GP_DLATCH and GP_DLATCHI	Andrew Zonenberg	2016-12-05	1	-0/+18
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*	Initial implementation of techlib support for GreenPAK latches. ↵	Andrew Zonenberg	2016-12-05	2	-0/+120
\| \| \| \|	Instantiation only, no behavioral inference yet.
*	Updated help text for synth_greenpak4	Andrew Zonenberg	2016-12-05	1	-0/+2
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*	Indenting fixes in gowin sim cell lib	Clifford Wolf	2016-11-08	1	-20/+28
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*	Added hex constant support to write_verilog	Clifford Wolf	2016-11-03	1	-1/+1
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*	iCE40 flow is not experimental anymore	Clifford Wolf	2016-11-01	1	-1/+1
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