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techlibs
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Author
Age
Files
Lines
*
Blackbox all whiteboxes after synthesis
gatecat
2021-03-17
15
-0
/
+15
*
memory_dff: Remove now-useless write port handling.
Marcelina Kościelnicka
2021-03-08
1
-6
/
+7
*
Fix syntax error in adff2dff.v
Marcelina Kościelnicka
2021-02-24
1
-1
/
+1
*
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ...
William D. Jones
2021-02-23
1
-11
/
+5
*
machxo2: Add experimental status to help.
William D. Jones
2021-02-23
1
-1
/
+1
*
machxo2: Add DCCA and DCMA blackbox primitives.
William D. Jones
2021-02-23
1
-0
/
+17
*
machxo2: Fix reversed interpretation of REG_SD config bits.
William D. Jones
2021-02-23
1
-2
/
+2
*
machxo2: Tristate is active-low.
William D. Jones
2021-02-23
2
-5
/
+5
*
machxo2: Fix typos in FACADE_FF sim model.
William D. Jones
2021-02-23
1
-5
/
+4
*
machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.
William D. Jones
2021-02-23
2
-6
/
+6
*
machxo2: Improve help_mode output in synth_machxo2.
William D. Jones
2021-02-23
1
-5
/
+5
*
machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to...
William D. Jones
2021-02-23
2
-1
/
+17
*
machxo2: Add missing OSCH oscillator primitive.
William D. Jones
2021-02-23
1
-0
/
+10
*
machxo2: Add -noiopad option to synth_machxo2.
William D. Jones
2021-02-23
1
-2
/
+11
*
machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.
William D. Jones
2021-02-23
1
-1
/
+1
*
machxo2: Fix cells_sim typo where OFX1 was multiply-driven.
William D. Jones
2021-02-23
1
-1
/
+1
*
machxo2: synth_machxo2 now maps ports to FACADE_IO.
William D. Jones
2021-02-23
2
-0
/
+12
*
machxo2: Add initial value for Q in FACADE_FF.
William D. Jones
2021-02-23
1
-0
/
+2
*
machxo2: Add FACADE_IO simulation model. More comments on models.
William D. Jones
2021-02-23
1
-0
/
+25
*
machxo2: Add FACADE_SLICE simulation model.
William D. Jones
2021-02-23
1
-0
/
+83
*
machxo2: Improve FACADE_FF simulation model.
William D. Jones
2021-02-23
1
-12
/
+20
*
machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.
William D. Jones
2021-02-23
2
-4
/
+4
*
machxo2: Add dff.ys test, fix another cells_map.v typo.
William D. Jones
2021-02-23
1
-1
/
+1
*
machxo2: Fix more oversights in machxo2 models. logic.ys test passes.
William D. Jones
2021-02-23
2
-2
/
+6
*
machxo2: Fix typos. test/arch/run-test.sh passes.
William D. Jones
2021-02-23
2
-2
/
+2
*
machxo2: Create basic techlibs and synth_machxo2 pass.
William D. Jones
2021-02-23
4
-0
/
+320
*
Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct
gatecat
2021-02-12
1
-0
/
+115
|
\
|
*
nexus: Add MULTADDSUB9X9WIDE sim model
David Shah
2020-12-08
1
-0
/
+115
*
|
verilog: significant block scoping improvements
Zachary Snow
2021-01-31
5
-81
/
+89
*
|
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
Marcelina Kościelnicka
2021-01-27
1
-3
/
+3
*
|
xilinx: Add FDRSE_1, FDCPE_1.
Marcelina Kościelnicka
2021-01-27
1
-0
/
+80
*
|
Fix some trivial typos.
Tom Verbeure
2021-01-03
1
-5
/
+5
*
|
Merge pull request #2480 from YosysHQ/dave/nexus-lram
whitequark
2021-01-01
5
-1
/
+227
|
\
|
|
*
nexus: Add LRAM inference
David Shah
2020-12-07
5
-1
/
+227
*
|
xilinx: Add some missing blackbox cells.
Marcelina Kościelnicka
2020-12-21
3
-798
/
+6276
*
|
xilinx: Regenerate cells_xtra.v using Vivado 2020.2
Marcelina Kościelnicka
2020-12-21
2
-42
/
+49
*
|
xilinx: Add FDDRCPE and FDDRRSE blackbox cells.
Marcelina Kościelnicka
2020-12-17
2
-0
/
+33
|
/
*
nexus: More efficient CO mapping
David Shah
2020-12-02
1
-2
/
+2
*
add -noalu and -json option for apicula
Pepijn de Vos
2020-11-30
1
-3
/
+32
*
nexus: DSP inference support
David Shah
2020-11-20
3
-1
/
+117
*
Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim
Miodrag Milanović
2020-11-18
3
-250
/
+573
|
\
|
*
nexus: Add DSP simulation model
David Shah
2020-11-18
3
-250
/
+573
*
|
Fix duplicated parameter name typo
Miodrag Milanovic
2020-11-18
1
-1
/
+1
*
|
synth_gowin: Add rPLL blackbox
Konrad Beckmann
2020-11-11
1
-0
/
+45
|
/
*
nexus: Add make_transp to BRAMs
David Shah
2020-10-22
1
-0
/
+3
*
Merge pull request #2405 from byuccl/fix_xilinx_cells
clairexen
2020-10-20
1
-2
/
+2
|
\
|
*
Move signal declarations to before first use
Jeff Goeders
2020-10-19
1
-2
/
+2
*
|
synth_nexus: Initial implementation
David Shah
2020-10-15
14
-0
/
+12229
|
/
*
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
Eddie Hung
2020-09-23
2
-17
/
+65
*
intel_alm: better map wide but shallow multiplies
Dan Ravensloft
2020-08-28
1
-2
/
+6
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