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| author | William D. Jones <thor0505@comcast.net> | 2021-01-31 19:05:15 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | a1ea1430b6ba478267d30253a79936fcb9e5faef (patch) | |
| tree | bc1ed0eda006567c6d61513152188b7274a006c9 /techlibs | |
| parent | 4e9def23de62c4e25478cdcaaba525d8686ac90c (diff) | |
| download | yosys-a1ea1430b6ba478267d30253a79936fcb9e5faef.tar.gz yosys-a1ea1430b6ba478267d30253a79936fcb9e5faef.tar.bz2 yosys-a1ea1430b6ba478267d30253a79936fcb9e5faef.zip | |
machxo2: Fix reversed interpretation of REG_SD config bits.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 5f985d477..e046d0c87 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -146,8 +146,8 @@ module FACADE_SLICE #( /* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F outputs (in other words, feeds back into FACADE_SLICE). */ - wire di0 = (REG0_SD == "1") ? M0 : DI0; - wire di1 = (REG1_SD == "1") ? M1 : DI1; + wire di0 = (REG0_SD == "1") ? DI0 : M0; + wire di1 = (REG1_SD == "1") ? DI1 : M1; FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET), |