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| author | Jeff Goeders <jeff.goeders@gmail.com> | 2020-10-19 16:09:04 -0600 |
|---|---|---|
| committer | Jeff Goeders <jeff.goeders@gmail.com> | 2020-10-19 16:09:18 -0600 |
| commit | 8be56960a26081ab57542d71fb78be594b9e014f (patch) | |
| tree | 02da426d69dc0148a85da507a363e24dc1baa5fb /techlibs | |
| parent | 1b7ed719a56896a582df5e6c2f904049cdcadc1f (diff) | |
| download | yosys-8be56960a26081ab57542d71fb78be594b9e014f.tar.gz yosys-8be56960a26081ab57542d71fb78be594b9e014f.tar.bz2 yosys-8be56960a26081ab57542d71fb78be594b9e014f.zip | |
Move signal declarations to before first use
Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 40804c367..4162160bb 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2335,6 +2335,8 @@ parameter integer PREG = 1; // The multiplier. wire signed [35:0] P_MULT; +wire signed [17:0] A_MULT; +wire signed [17:0] B_MULT; assign P_MULT = A_MULT * B_MULT; // The cascade output. @@ -2373,8 +2375,6 @@ always @(posedge CLK) begin end // The register enables. -wire signed [17:0] A_MULT; -wire signed [17:0] B_MULT; assign A_MULT = (AREG == 1) ? A_REG : A; assign B_MULT = (BREG == 1) ? B_REG : B_MUX; assign P = (PREG == 1) ? P_REG : P_MULT; |