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author | Pepijn de Vos <pepijndevos@gmail.com> | 2020-11-30 11:43:12 +0100 |
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committer | Pepijn de Vos <pepijndevos@gmail.com> | 2020-11-30 11:43:12 +0100 |
commit | f155826a706657fc082cfbc41bb714f733e82a53 (patch) | |
tree | 1003dc5a27e993b85262cb9f04926f800ec83d90 /techlibs | |
parent | 2116c585810cddb73777b46ea9aad0d6d511d82b (diff) | |
download | yosys-f155826a706657fc082cfbc41bb714f733e82a53.tar.gz yosys-f155826a706657fc082cfbc41bb714f733e82a53.tar.bz2 yosys-f155826a706657fc082cfbc41bb714f733e82a53.zip |
add -noalu and -json option for apicula
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/gowin/synth_gowin.cc | 35 |
1 files changed, 32 insertions, 3 deletions
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 4d1e968ae..5bf0894da 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -44,6 +44,11 @@ struct SynthGowinPass : public ScriptPass log(" write the design to the specified Verilog netlist file. writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); log("\n"); + log(" -json <file>\n"); + log(" write the design to the specified JSON netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); + log(" This disables features not yet supported by nexpnr-gowin.\n"); + log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -70,6 +75,9 @@ struct SynthGowinPass : public ScriptPass log(" -noiopads\n"); log(" do not emit IOB at top level ports\n"); log("\n"); + log(" -noalu\n"); + log(" do not use ALU cells\n"); + log("\n"); log(" -abc9\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); @@ -79,13 +87,14 @@ struct SynthGowinPass : public ScriptPass log("\n"); } - string top_opt, vout_file; - bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads; + string top_opt, vout_file, json_file; + bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads, noalu; void clear_flags() override { top_opt = "-auto-top"; vout_file = ""; + json_file = ""; retime = false; flatten = true; nobram = false; @@ -94,6 +103,7 @@ struct SynthGowinPass : public ScriptPass nowidelut = false; abc9 = false; noiopads = false; + noalu = false; } void execute(std::vector<std::string> args, RTLIL::Design *design) override @@ -112,6 +122,14 @@ struct SynthGowinPass : public ScriptPass vout_file = args[++argidx]; continue; } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + nobram = true; + nolutram = true; + nowidelut = true; + noalu = true; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) @@ -144,6 +162,10 @@ struct SynthGowinPass : public ScriptPass nowidelut = true; continue; } + if (args[argidx] == "-noalu") { + noalu = true; + continue; + } if (args[argidx] == "-abc9") { abc9 = true; continue; @@ -210,7 +232,11 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_gates")) { - run("techmap -map +/techmap.v -map +/gowin/arith_map.v"); + if (noalu) { + run("techmap -map +/techmap.v"); + } else { + run("techmap -map +/techmap.v -map +/gowin/arith_map.v"); + } run("opt -fast"); if (retime || help_mode) run("abc -dff -D 1", "(only if -retime)"); @@ -270,6 +296,9 @@ struct SynthGowinPass : public ScriptPass if (!vout_file.empty() || help_mode) run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s", help_mode ? "<file-name>" : vout_file.c_str())); + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", + help_mode ? "<file-name>" : json_file.c_str())); } } } SynthGowinPass; |