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| author | William D. Jones <thor0505@comcast.net> | 2020-11-17 14:22:44 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | 044393b990316d997df3a5cc57e9d065c3a5e9d8 (patch) | |
| tree | 5e3fef5be6fcf83c1e3caab1504f26b2d504208a /techlibs | |
| parent | 9cb0bae1b27928202fa9ce6d494f7f6aaa36563a (diff) | |
| download | yosys-044393b990316d997df3a5cc57e9d065c3a5e9d8.tar.gz yosys-044393b990316d997df3a5cc57e9d065c3a5e9d8.tar.bz2 yosys-044393b990316d997df3a5cc57e9d065c3a5e9d8.zip | |
machxo2: Fix more oversights in machxo2 models. logic.ys test passes.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/machxo2/cells_map.v | 6 | ||||
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 2 |
2 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/machxo2/cells_map.v b/techlibs/machxo2/cells_map.v index 0f21fc32b..345675db9 100644 --- a/techlibs/machxo2/cells_map.v +++ b/techlibs/machxo2/cells_map.v @@ -8,12 +8,16 @@ module \$lut (A, Y); wire [3:0] I; generate - if(WIDTH == 2) begin + if(WIDTH == 1) begin + assign I = {1'b0, 1'b0, 1'b0, A[0]}; + end else if(WIDTH == 2) begin assign I = {1'b0, 1'b0, A[1], A[0]}; end else if(WIDTH == 3) begin assign I = {1'b0, A[2], A[1], A[0]}; end else if(WIDTH == 4) begin assign I = {A[3], A[2], A[1], A[0]}; + end else begin + INVALID_LUT_WIDTH error(); end endgenerate diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 22b4fcf3c..8db73c50c 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -42,7 +42,7 @@ module FACADE_FF #( wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; - assign srval = (REGSET == "SET") ? 1'b1 : 1'b0; + wire srval = (REGSET == "SET") ? 1'b1 : 1'b0; generate if (SRMODE == "ASYNC") begin |