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| author | William D. Jones <thor0505@comcast.net> | 2020-11-21 18:44:42 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | 03cbf1327d01dbb7997d2f2b241340c29ff35e00 (patch) | |
| tree | 785425cff3eac088ad5fd91184a548443a8c6162 /techlibs | |
| parent | 0364ded385e3ba7817a9e466e165a184292c3ef2 (diff) | |
| download | yosys-03cbf1327d01dbb7997d2f2b241340c29ff35e00.tar.gz yosys-03cbf1327d01dbb7997d2f2b241340c29ff35e00.tar.bz2 yosys-03cbf1327d01dbb7997d2f2b241340c29ff35e00.zip | |
machxo2: Add initial value for Q in FACADE_FF.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index f09837c13..ef40f0231 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -46,6 +46,8 @@ module FACADE_FF #( wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; wire srval = (REGSET == "SET") ? 1'b1 : 1'b0; + initial Q = srval; + generate if (REGMODE == "FF") begin if (SRMODE == "ASYNC") begin |