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| author | William D. Jones <thor0505@comcast.net> | 2020-11-20 21:24:39 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | cc52eb53cde6863ae209343c234c33e1092e94b6 (patch) | |
| tree | d11fa4b97087521bd049aacca7532b632f9c44e6 /techlibs | |
| parent | 427fed23eec2f09eb93bf08a5ac1a4cd41d0a2c2 (diff) | |
| download | yosys-cc52eb53cde6863ae209343c234c33e1092e94b6.tar.gz yosys-cc52eb53cde6863ae209343c234c33e1092e94b6.tar.bz2 yosys-cc52eb53cde6863ae209343c234c33e1092e94b6.zip | |
machxo2: Improve FACADE_FF simulation model.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 32 |
1 files changed, 20 insertions, 12 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 2c4d2f462..8d93a4a33 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -24,7 +24,8 @@ module FACADE_FF #( parameter LSRMUX = "LSR", parameter LSRONMUX = "LSRMUX", parameter SRMODE = "LSR_OVER_CE", - parameter REGSET = "SET" + parameter REGSET = "SET", + parameter REGMODE = "FF" ) ( input CLK, DI, LSR, CE, output reg Q @@ -41,22 +42,29 @@ module FACADE_FF #( endgenerate wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; + wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; wire srval = (REGSET == "SET") ? 1'b1 : 1'b0; generate - if (SRMODE == "ASYNC") begin - always @(posedge muxclk, posedge muxlsr) - if (muxlsr) - Q <= srval; - else if (muxce) - Q <= DI; + if (REGMODE == "FF") begin + if (SRMODE == "ASYNC") begin + always @(posedge muxclk, posedge muxlsron) + if (muxlsron) + Q <= srval; + else if (muxce) + Q <= DI; + end else begin + always @(posedge muxclk) + if (muxlsron) + Q <= srval; + else if (muxce) + Q <= DI; + end + end else if (REGMODE == "LATCH") begin + ERROR_UNSUPPORTED_FF_MODE error(); end else begin - always @(posedge muxclk) - if (muxlsr) - Q <= srval; - else if (muxce) - Q <= DI; + ERROR_UNKNOWN_FF_MODE error(); end endgenerate endmodule |