iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	abc9: replace cell type/parameters if derived type already processed (#2991)	Eddie Hung	2021-09-09	1	-1/+1
*	[ECP5] fix wrong link for syn_* attributes description (#2984)	kittennbfive	2021-08-29	2	-2/+2
*	Add DLLDELD	ECP5-PCIe	2021-08-22	1	-0/+9
*	Gowin: deal with active-low tristate (#2971)	Pepijn de Vos	2021-08-20	4	-6/+13
*	ice40: Fix typo in SB_CARRY specify for LP/UltraPlus	Sylvain Munaut	2021-08-17	1	-2/+2
*	Add v2 memory cells.	Marcelina Kościelnicka	2021-08-11	1	-0/+169
*	Fixes xc7 BRAM36s	Maciej Dudek	2021-07-30	1	-4/+6
*	opt_lut: Allow more than one -dlogic per cell type.	Marcelina Kościelnicka	2021-07-29	1	-1/+1
*	memory: Introduce $meminit_v2 cell, with EN input.	Marcelina Kościelnicka	2021-07-28	1	-0/+24
*	ice40: Fix LUT input indices in opt_lut -dlogic (again).	Marcelina Kościelnicka	2021-07-10	1	-1/+1
*	ecp5: Add DCSC blackbox	gatecat	2021-07-06	1	-0/+10
*	Fix icestorm links	Claire Xenia Wolf	2021-06-09	2	-516/+516
*	Use HTTPS for website links, gatecat email	Claire Xenia Wolf	2021-06-09	6	-6/+6
*	Fix files with CRLF line endings	Claire Xenia Wolf	2021-06-09	2	-349/+349
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	58	-64/+64
*	intel_alm: Fix illegal carry chains	gatecat	2021-05-15	2	-3/+5
*	intel_alm: Add global buffer insertion	gatecat	2021-05-15	6	-4/+78
*	intel_alm: Add IO buffer insertion	gatecat	2021-05-15	6	-7/+127
*	Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.	Adam Greig	2021-05-12	1	-0/+22
*	Fix use of blif name in synth_xilinx command	Michael Christensen	2021-04-27	1	-1/+1
*	Add default assignments to other SB_* simulation models	Claire Xenia Wolf	2021-04-20	1	-24/+44
*	Add default assignments to SB_LUT4	Claire Xenia Wolf	2021-04-20	1	-1/+17
*	quicklogic: ABC9 synthesis	Lofty	2021-04-17	6	-5/+80
*	sf2: fix name of AND modules	Stefan Riesenberger	2021-04-09	1	-3/+3
*	abc9: fix SCC issues (#2694)	Eddie Hung	2021-03-29	2	-0/+9
*	quicklogic: PolarPro 3 support	Lofty	2021-03-18	9	-0/+770
*	Blackbox all whiteboxes after synthesis	gatecat	2021-03-17	15	-0/+15
*	memory_dff: Remove now-useless write port handling.	Marcelina Kościelnicka	2021-03-08	1	-6/+7
*	Fix syntax error in adff2dff.v	Marcelina Kościelnicka	2021-02-24	1	-1/+1
*	machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ...	William D. Jones	2021-02-23	1	-11/+5
*	machxo2: Add experimental status to help.	William D. Jones	2021-02-23	1	-1/+1
*	machxo2: Add DCCA and DCMA blackbox primitives.	William D. Jones	2021-02-23	1	-0/+17
*	machxo2: Fix reversed interpretation of REG_SD config bits.	William D. Jones	2021-02-23	1	-2/+2
*	machxo2: Tristate is active-low.	William D. Jones	2021-02-23	2	-5/+5
*	machxo2: Fix typos in FACADE_FF sim model.	William D. Jones	2021-02-23	1	-5/+4
*	machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.	William D. Jones	2021-02-23	2	-6/+6
*	machxo2: Improve help_mode output in synth_machxo2.	William D. Jones	2021-02-23	1	-5/+5
*	machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to...	William D. Jones	2021-02-23	2	-1/+17
*	machxo2: Add missing OSCH oscillator primitive.	William D. Jones	2021-02-23	1	-0/+10
*	machxo2: Add -noiopad option to synth_machxo2.	William D. Jones	2021-02-23	1	-2/+11
*	machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.	William D. Jones	2021-02-23	1	-1/+1
*	machxo2: Fix cells_sim typo where OFX1 was multiply-driven.	William D. Jones	2021-02-23	1	-1/+1
*	machxo2: synth_machxo2 now maps ports to FACADE_IO.	William D. Jones	2021-02-23	2	-0/+12
*	machxo2: Add initial value for Q in FACADE_FF.	William D. Jones	2021-02-23	1	-0/+2
*	machxo2: Add FACADE_IO simulation model. More comments on models.	William D. Jones	2021-02-23	1	-0/+25
*	machxo2: Add FACADE_SLICE simulation model.	William D. Jones	2021-02-23	1	-0/+83
*	machxo2: Improve FACADE_FF simulation model.	William D. Jones	2021-02-23	1	-12/+20
*	machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.	William D. Jones	2021-02-23	2	-4/+4
*	machxo2: Add dff.ys test, fix another cells_map.v typo.	William D. Jones	2021-02-23	1	-1/+1
*	machxo2: Fix more oversights in machxo2 models. logic.ys test passes.	William D. Jones	2021-02-23	2	-2/+6