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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-21 02:26:52 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-07-28 23:18:38 +0200 |
| commit | 19720b970dff017c47805e37745b9fcf29843c45 (patch) | |
| tree | b5a56d888b9e8c7530fc456a8748c32bb3feaed3 /techlibs | |
| parent | 37d76deef1229048e145d77b5c75bcc2e0e1cf44 (diff) | |
| download | yosys-19720b970dff017c47805e37745b9fcf29843c45.tar.gz yosys-19720b970dff017c47805e37745b9fcf29843c45.tar.bz2 yosys-19720b970dff017c47805e37745b9fcf29843c45.zip | |
memory: Introduce $meminit_v2 cell, with EN input.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 42a355c2d..ad654c8a4 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -2233,6 +2233,30 @@ endmodule // -------------------------------------------------------- +module \$meminit_v2 (ADDR, DATA, EN); + +parameter MEMID = ""; +parameter ABITS = 8; +parameter WIDTH = 8; +parameter WORDS = 1; + +parameter PRIORITY = 0; + +input [ABITS-1:0] ADDR; +input [WORDS*WIDTH-1:0] DATA; +input [WIDTH-1:0] EN; + +initial begin + if (MEMID != "") begin + $display("ERROR: Found non-simulatable instance of $meminit_v2!"); + $finish; + end +end + +endmodule + +// -------------------------------------------------------- + module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter MEMID = ""; |