intel_alm: Add IO buffer insertion

Signed-off-by: gatecat <gatecat@ds0.me>

6 files changed, 127 insertions, 7 deletions

diff --git a/techlibs/intel_alm/Makefile.inc b/techlibs/intel_alm/Makefile.inc
index da88762c4..614d5802c 100644
--- a/techlibs/intel_alm/Makefile.inc
+++ b/techlibs/intel_alm/Makefile.inc
@@ -13,6 +13,7 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/df
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_sim.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_map.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
+$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/misc_sim.v))
 
 $(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclonev/cells_sim.v))
 
diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v
index 874f293b1..aabcd4539 100644
--- a/techlibs/intel_alm/common/megafunction_bb.v
+++ b/techlibs/intel_alm/common/megafunction_bb.v
@@ -627,3 +627,38 @@ output [port_b_data_width-1:0] portbdataout;
 input clk0, portawe, portbre;
 
 endmodule
+
+(* blackbox *)
+module cyclone10gx_io_ibuf(i, ibar, dynamicterminationcontrol, o);
+
+parameter differential_mode ="false";
+parameter bus_hold = "false";
+parameter simulate_z_as = "Z";
+parameter lpm_type = "cyclone10gx_io_ibuf";
+
+(* iopad_external_pin *) input i;
+(* iopad_external_pin *) input ibar;
+input dynamicterminationcontrol;
+output o;
+
+endmodule
+
+(* blackbox *)
+module cyclone10gx_io_obuf(i, oe, dynamicterminationcontrol, seriesterminationcontrol, parallelterminationcontrol, devoe, o, obar);
+
+parameter open_drain_output = "false";
+parameter bus_hold = "false";
+parameter shift_series_termination_control = "false";
+parameter sim_dynamic_termination_control_is_connected = "false";
+parameter lpm_type = "cyclone10gx_io_obuf";
+
+input i;
+input oe;
+input devoe;
+input dynamicterminationcontrol;
+input [15:0] seriesterminationcontrol;
+input [15:0] parallelterminationcontrol;
+(* iopad_external_pin *) output o;
+(* iopad_external_pin *) output obar;
+
+endmodule
diff --git a/techlibs/intel_alm/common/misc_sim.v b/techlibs/intel_alm/common/misc_sim.v
new file mode 100644
index 000000000..e9494a8ee
--- /dev/null
+++ b/techlibs/intel_alm/common/misc_sim.v
@@ -0,0 +1,12 @@
+module MISTRAL_IB((* iopad_external_pin *)  input PAD, output O);
+	assign O = PAD;
+endmodule
+
+module MISTRAL_OB((* iopad_external_pin *)  output PAD, input I);
+	assign PAD = I;
+endmodule
+
+module MISTRAL_IO((* iopad_external_pin *)  inout PAD, input I, input OE, output O);
+	assign PAD = OE ? I : 1'bz;
+	assign O = PAD;
+endmodule
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
index 3b4628675..964a094dd 100644
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ b/techlibs/intel_alm/common/quartus_rename.v
@@ -2,11 +2,15 @@
 `define LCELL cyclonev_lcell_comb
 `define MAC cyclonev_mac
 `define MLAB cyclonev_mlab_cell
+`define IBUF cyclonev_io_ibuf
+`define OBUF cyclonev_io_obuf
 `endif
 `ifdef cyclone10gx
 `define LCELL cyclone10gx_lcell_comb
 `define MAC cyclone10gx_mac
 `define MLAB cyclone10gx_mlab_cell
+`define IBUF cyclone10gx_io_ibuf
+`define OBUF cyclone10gx_io_obuf
 `endif
 
 module __MISTRAL_VCC(output Q);
@@ -233,3 +237,43 @@ parameter B_SIGNED = 1;
 );
 
 endmodule
+
+module MISTRAL_IB(input PAD, output O);
+`IBUF #(
+    .bus_hold("false"),
+    .differential_mode("false")
+) _TECHMAP_REPLACE_ (
+    .i(PAD),
+    .o(O)
+);
+endmodule
+
+module MISTRAL_OB(output PAD, input I, OE);
+`OBUF #(
+    .bus_hold("false"),
+    .differential_mode("false")
+) _TECHMAP_REPLACE_ (
+    .i(I),
+    .o(PAD),
+    .oe(OE)
+);
+endmodule
+
+module MISTRAL_IO(output PAD, input I, OE, output O);
+`IBUF #(
+    .bus_hold("false"),
+    .differential_mode("false")
+) ibuf (
+    .i(PAD),
+    .o(O)
+);
+
+`OBUF #(
+    .bus_hold("false"),
+    .differential_mode("false")
+) obuf (
+    .i(I),
+    .o(PAD),
+    .oe(OE)
+);
+endmodule
diff --git a/techlibs/intel_alm/cyclonev/cells_sim.v b/techlibs/intel_alm/cyclonev/cells_sim.v
index 9b2a10e72..d0a9d9179 100644
--- a/techlibs/intel_alm/cyclonev/cells_sim.v
+++ b/techlibs/intel_alm/cyclonev/cells_sim.v
@@ -26,16 +26,34 @@ endmodule // GND
 
 /* Altera Cyclone V devices Input Buffer Primitive */
 module cyclonev_io_ibuf
-  (output o, input i, input ibar);
-   assign ibar = ibar;
+  (output o,
+   (* iopad_external_pin *) input i,
+   (* iopad_external_pin *) input ibar,
+   input dynamicterminationcontrol);
+
+   parameter differential_mode = "false";
+   parameter bus_hold = "false";
+   parameter simulate_z_as = "Z";
+   parameter lpm_type = "cyclonev_io_ibuf";
+
    assign o    = i;
 endmodule // cyclonev_io_ibuf
 
 /* Altera Cyclone V devices Output Buffer Primitive */
 module cyclonev_io_obuf
-  (output o, input i, input oe);
-   assign o  = i;
-   assign oe = oe;
+  ((* iopad_external_pin *) output o,
+   input i, oe, dynamicterminationcontrol,
+   input [15:0] seriesterminationcontrol, parallelterminationcontrol,
+   input devoe,
+   (* iopad_external_pin *) output obar);
+
+   parameter open_drain_output = "false";
+   parameter bus_hold = "false";
+   parameter shift_series_termination_control = "false";
+   parameter sim_dynamic_termination_control_is_connected = "false";
+   parameter lpm_type = "cyclonev_io_obuf";
+
+   assign o  = oe ? i : 1'bz;
 endmodule // cyclonev_io_obuf
 
 /* Altera Cyclone V LUT Primitive */
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 11b6d0525..7c9e3d117 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -72,13 +72,16 @@ struct SynthIntelALMPass : public ScriptPass {
 		log("    -nodsp\n");
 		log("        do not map multipliers to MISTRAL_MUL cells\n");
 		log("\n");
+		log("    -noiopad\n");
+		log("        do not instantiate IO buffers\n");
+		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
 		log("\n");
 	}
 
 	string top_opt, family_opt, bram_type, vout_file;
-	bool flatten, quartus, nolutram, nobram, dff, nodsp;
+	bool flatten, quartus, nolutram, nobram, dff, nodsp, noiopad;
 
 	void clear_flags() override
 	{
@@ -92,6 +95,7 @@ struct SynthIntelALMPass : public ScriptPass {
 		nobram = false;
 		dff = false;
 		nodsp = false;
+		noiopad = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -146,6 +150,10 @@ struct SynthIntelALMPass : public ScriptPass {
 				dff = true;
 				continue;
 			}
+			if (args[argidx] == "-noiopad") {
+				noiopad = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -183,8 +191,8 @@ struct SynthIntelALMPass : public ScriptPass {
 			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str()));
+			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt.c_str()));
-
 			// Misc and common cells
 			run("read_verilog -lib +/intel/common/altpll_bb.v");
 			run("read_verilog -lib +/intel_alm/common/megafunction_bb.v");
@@ -231,6 +239,8 @@ struct SynthIntelALMPass : public ScriptPass {
 				}
 			}
 			run("alumacc");
+			if (!noiopad)
+				run("iopadmap -bits -outpad MISTRAL_OB I:PAD -inpad MISTRAL_IB O:PAD -toutpad MISTRAL_IO OE:O:PAD -tinoutpad MISTRAL_IO OE:O:I:PAD A:top", "(unless -noiopad)");
 			run("techmap -map +/intel_alm/common/arith_alm_map.v -map +/intel_alm/common/dsp_map.v");
 			run("opt");
 			run("memory -nomap");