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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-0520-91/+531
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| * Resolve TODO with pin assignments for SRL*Eddie Hung2019-09-041-4/+2
| * Add commentsEddie Hung2019-09-021-1/+9
| * Rename boxEddie Hung2019-09-021-1/+1
| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-09-022-7/+8
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| * | Remove trailing spaceEddie Hung2019-08-301-2/+2
| * | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-3010-109/+150
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| * | | Use a dummy box file if none specifiedEddie Hung2019-08-282-0/+2
| * | | Comment out SB_MAC16 arrival time for now, need to handle all its modesEddie Hung2019-08-281-1/+1
| * | | Add arrival for SB_MAC16.OEddie Hung2019-08-281-0/+1
| * | | Add arrival times for UEddie Hung2019-08-281-0/+26
| * | | LX -> LPEddie Hung2019-08-281-1/+1
| * | | Round not floorEddie Hung2019-08-281-21/+21
| * | | Add LP timingsEddie Hung2019-08-281-0/+26
| * | | LX -> LPEddie Hung2019-08-281-1/+1
| * | | Do not overwrite LUT paramEddie Hung2019-08-281-1/+0
| * | | Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrivalEddie Hung2019-08-282-1/+48
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| * | | | Add arrival times for HX devicesEddie Hung2019-08-281-21/+114
| * | | | Specify ice40 family to cells_sim.v using defineEddie Hung2019-08-281-1/+8
| * | | | Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrivalEddie Hung2019-08-285-68/+20
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| * \ \ \ \ Merge branch 'eddie/xilinx_srl' into xaig_arrivalEddie Hung2019-08-281-15/+22
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| * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-2813-249/+865
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| * | | | | | | Fix spacingEddie Hung2019-08-231-1/+1
| * | | | | | | Remove unused modelEddie Hung2019-08-231-13/+0
| * | | | | | | Put attributes above portEddie Hung2019-08-232-27/+62
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-2317-102/+981
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| * | | | | | | | Use semicolonEddie Hung2019-08-211-1/+1
| * | | | | | | | techmap before readEddie Hung2019-08-211-1/+1
| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-211-1/+1
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| * | | | | | | | | Add abc_arrival to SRL*Eddie Hung2019-08-211-3/+5
| * | | | | | | | | OopsEddie Hung2019-08-201-1/+1
| * | | | | | | | | xilinx to use abc_map.v with -max_iter 1Eddie Hung2019-08-206-171/+26
| * | | | | | | | | ecp5: remove DPR16X4 from abc_unmap.vEddie Hung2019-08-201-20/+0
| * | | | | | | | | ecp5 to use -max_iter 1Eddie Hung2019-08-203-4/+3
| * | | | | | | | | ecp5 to use abc_map.v and _unmap.vEddie Hung2019-08-207-14/+89
| * | | | | | | | | Add reference to FD* timingEddie Hung2019-08-201-0/+2
| * | | | | | | | | Remove sequential extensionEddie Hung2019-08-206-359/+17
| * | | | | | | | | Remove SRL* delays from cells_sim.vEddie Hung2019-08-201-5/+3
| * | | | | | | | | LUTMUX -> LUTMUX6Eddie Hung2019-08-201-2/+2
| * | | | | | | | | Cleanup techmap in map_lutsEddie Hung2019-08-201-3/+5
| * | | | | | | | | Move `techmap abc_map.v` into map_lutsEddie Hung2019-08-201-1/+2
| * | | | | | | | | Remove delays from abc_map.vEddie Hung2019-08-201-5/+2
| * | | | | | | | | TypoEddie Hung2019-08-201-1/+1
| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-204-16/+19
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| * | | | | | | | | | Wrap SRL{16,32} tooEddie Hung2019-08-203-7/+98
| * | | | | | | | | | Wrap LUTRAMs in order to capture comb/seq behaviourEddie Hung2019-08-205-36/+200
| * | | | | | | | | | Add LUTRAM delaysEddie Hung2019-08-201-3/+6
| * | | | | | | | | | Remove mapping rulesEddie Hung2019-08-201-33/+0
| * | | | | | | | | | Remove -icellsEddie Hung2019-08-201-2/+2
| * | | | | | | | | | Use abc_{map,unmap,model}.vEddie Hung2019-08-207-110/+324