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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 18:51:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 18:51:14 -0700 |
| commit | e3709e5ee6b28c1156b4768373e244c32c7c5aba (patch) | |
| tree | 6cc5f4b4e52e43c6f7c07900679de04029c5644a /techlibs | |
| parent | 5c42455350740cbdc8f12ba912eb32398c61e9fb (diff) | |
| download | yosys-e3709e5ee6b28c1156b4768373e244c32c7c5aba.tar.gz yosys-e3709e5ee6b28c1156b4768373e244c32c7c5aba.tar.bz2 yosys-e3709e5ee6b28c1156b4768373e244c32c7c5aba.zip | |
LX -> LP
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 34134d02a..fe80c998d 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -3,7 +3,7 @@ // `define SB_DFF_REG reg Q `define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif -`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif +`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif `define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif // SiliconBlue IO Cells |