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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:31:20 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:31:20 -0700 |
commit | e658d472c89d0fef820f2a9ddc6184b566cc0d9b (patch) | |
tree | da7f4c319acd0c0a08f8064feee07595da8e0c5d /techlibs | |
parent | d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5 (diff) | |
download | yosys-e658d472c89d0fef820f2a9ddc6184b566cc0d9b.tar.gz yosys-e658d472c89d0fef820f2a9ddc6184b566cc0d9b.tar.bz2 yosys-e658d472c89d0fef820f2a9ddc6184b566cc0d9b.zip |
Put attributes above port
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/cells_sim.v | 65 | ||||
-rw-r--r-- | techlibs/xilinx/xc7_brams_bb.v | 24 |
2 files changed, 62 insertions, 27 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 21ac19300..e2ec4e525 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -215,8 +215,11 @@ endmodule // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 -module FDRE ((* abc_arrival=303 *) output reg Q, - input C, CE, D, R); +module FDRE ( + (* abc_arrival=303 *) + output reg Q, + input C, CE, D, R +); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -228,8 +231,11 @@ module FDRE ((* abc_arrival=303 *) output reg Q, endcase endgenerate endmodule -module FDSE ((* abc_arrival=303 *) output reg Q, - input C, CE, D, S); +module FDSE ( + (* abc_arrival=303 *) + output reg Q, + input C, CE, D, S +); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -241,8 +247,11 @@ module FDSE ((* abc_arrival=303 *) output reg Q, endcase endgenerate endmodule -module FDCE ((* abc_arrival=303 *) output reg Q, - input C, CE, D, CLR); +module FDCE ( + (* abc_arrival=303 *) + output reg Q, + input C, CE, D, CLR +); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -256,8 +265,11 @@ module FDCE ((* abc_arrival=303 *) output reg Q, endcase endgenerate endmodule -module FDPE ((* abc_arrival=303 *) output reg Q, - input C, CE, D, PRE); +module FDPE ( + (* abc_arrival=303 *) + output reg Q, + input C, CE, D, PRE +); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -271,29 +283,41 @@ module FDPE ((* abc_arrival=303 *) output reg Q, endcase endgenerate endmodule -module FDRE_1 ((* abc_arrival=303 *) output reg Q, - input C, CE, D, R); +module FDRE_1 ( + (* abc_arrival=303 *) + output reg Q, + input C, CE, D, R +); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; endmodule -module FDSE_1 ((* abc_arrival=303 *) output reg Q, - input C, CE, D, S); +module FDSE_1 ( + (* abc_arrival=303 *) + output reg Q, + input C, CE, D, S +); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; endmodule -module FDCE_1 ((* abc_arrival=303 *) output reg Q, - input C, CE, D, CLR); +module FDCE_1 ( + (* abc_arrival=303 *) + output reg Q, + input C, CE, D, CLR +); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; endmodule -module FDPE_1 ((* abc_arrival=303 *) output reg Q, - input C, CE, D, PRE); +module FDPE_1 ( + (* abc_arrival=303 *) + output reg Q, + input C, CE, D, PRE +); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; @@ -361,7 +385,8 @@ endmodule module SRL16E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output Q, + (* abc_arrival=1472 *) + output Q, input A0, A1, A2, A3, CE, CLK, D ); parameter [15:0] INIT = 16'h0000; @@ -380,8 +405,10 @@ endmodule module SRLC32E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output Q, - (* abc_arrival=1114 *) output Q31, + (* abc_arrival=1472 *) + output Q, + (* abc_arrival=1114 *) + output Q31, input [4:0] A, input CE, CLK, D ); diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v index 0e8cb406c..56939089c 100644 --- a/techlibs/xilinx/xc7_brams_bb.v +++ b/techlibs/xilinx/xc7_brams_bb.v @@ -21,10 +21,14 @@ module RAMB18E1 ( input [1:0] WEA, input [3:0] WEBWE, - (* abc_arrival=2454 *) output [15:0] DOADO, - (* abc_arrival=2454 *) output [15:0] DOBDO, - (* abc_arrival=2454 *) output [1:0] DOPADOP, - (* abc_arrival=2454 *) output [1:0] DOPBDOP + (* abc_arrival=2454 *) + output [15:0] DOADO, + (* abc_arrival=2454 *) + output [15:0] DOBDO, + (* abc_arrival=2454 *) + output [1:0] DOPADOP, + (* abc_arrival=2454 *) + output [1:0] DOPBDOP ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -145,10 +149,14 @@ module RAMB36E1 ( input [3:0] WEA, input [7:0] WEBWE, - (* abc_arrival=2454 *) output [31:0] DOADO, - (* abc_arrival=2454 *) output [31:0] DOBDO, - (* abc_arrival=2454 *) output [3:0] DOPADOP, - (* abc_arrival=2454 *) output [3:0] DOPBDOP + (* abc_arrival=2454 *) + output [31:0] DOADO, + (* abc_arrival=2454 *) + output [31:0] DOBDO, + (* abc_arrival=2454 *) + output [3:0] DOPADOP, + (* abc_arrival=2454 *) + output [3:0] DOPBDOP ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |