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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:08:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:08:07 -0700 |
| commit | aa2d3af6319d475e589acd1efc83d07c11257229 (patch) | |
| tree | d63efc888c2aff743154ac2a9b6ac5fb60c4560c /techlibs | |
| parent | 30a379b5b6600f0e0e99f0c99ad7bc1d4d08cd90 (diff) | |
| download | yosys-aa2d3af6319d475e589acd1efc83d07c11257229.tar.gz yosys-aa2d3af6319d475e589acd1efc83d07c11257229.tar.bz2 yosys-aa2d3af6319d475e589acd1efc83d07c11257229.zip | |
LUTMUX -> LUTMUX6
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 1d8604ddb..a760b3d6d 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -136,8 +136,8 @@ module RAM32X1D ( .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4) ); - \$__ABC_LUTMUX dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO)); - \$__ABC_LUTMUX spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO)); + \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO)); + \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO)); endmodule module RAM64X1D ( |