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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 17:21:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 17:21:12 -0700 |
| commit | e4f89e01b5710eb9e2e6675a1df13a5a2637b206 (patch) | |
| tree | ffc83680a39e74ae6db4691ed6b018bb4dfa66a8 /techlibs | |
| parent | 345a572449d64749c77eb11b401a2372c94bead8 (diff) | |
| download | yosys-e4f89e01b5710eb9e2e6675a1df13a5a2637b206.tar.gz yosys-e4f89e01b5710eb9e2e6675a1df13a5a2637b206.tar.bz2 yosys-e4f89e01b5710eb9e2e6675a1df13a5a2637b206.zip | |
Specify ice40 family to cells_sim.v using define
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index c6de81bd9..2f77c03db 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -icells -lib +/ice40/cells_sim.v"); + std::string define; + if (device_opt == "lp") + define = "-D ICE40_LX"; + else if (device_opt == "u") + define = "-D ICE40_U"; + else + define = "-D ICE40_HX"; + run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } |