iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Merge pull request #1648 from YosysHQ/eddie/cmp2lcu	Eddie Hung	2020-04-03	4	-11/+120
\|\ \| \| \| \|	"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
\| *	cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp	Eddie Hung	2020-04-03	1	-1/+1
\| \|
\| *	cmp2lcu: fail if `LUT_WIDTH < 2	Eddie Hung	2020-04-03	1	-1/+1
\| \|
\| *	synth: only techmap cmp2{lut,lcu} if -lut	Eddie Hung	2020-04-03	1	-1/+1
\| \|
\| *	synth: use +/cmp2lcu.v in generic 'synth' too	Eddie Hung	2020-04-03	1	-2/+2
\| \|
\| *	Cleanup +/cmp2lut.v	Eddie Hung	2020-04-03	1	-8/+0
\| \|
\| *	+/cmp2lcu.v to work efficiently for fully/partially constant inputs	Eddie Hung	2020-04-03	1	-33/+42
\| \|
\| *	Refactor +/cmp2lcu.v into recursive techmap	Eddie Hung	2020-04-03	1	-38/+65
\| \|
\| *	Cleanup	Eddie Hung	2020-04-03	1	-31/+28
\| \|
\| *	Cleanup cmp2lcu.v	Eddie Hung	2020-04-03	1	-16/+16
\| \|
\| *	techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu	Eddie Hung	2020-04-03	2	-0/+84
\| \|
\| *	cmp2lut: comment out unused since 362f4f9	Eddie Hung	2020-04-03	1	-8/+8
\| \|
* \|	simcells.v: Generate the fine FF cell types by a python script.	Marcin Kościelnicki	2020-04-02	2	-19/+270
\|/ \| \| \| \| \|	This makes adding more FF types in the future much more manageable. Fixes #1824.
*	Fix invalid verilog syntax	Miodrag Milanovic	2020-03-14	1	-1/+1
\|
*	Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc	N. Engelhardt	2020-03-03	1	-2/+17
\|\ \| \| \| \|	Add -flowmap option to `synth{,_ice40}`
\| *	Add -flowmap to synth and synth_ice40	Dan Ravensloft	2020-02-28	1	-2/+17
\| \|
* \|	Create +/abc9_model.v for $__ABC9_{DELAY,FF_}	Eddie Hung	2020-02-27	2	-0/+11
\|/
*	techmap: fix shiftx2mux decomposition	Eddie Hung	2020-02-07	1	-8/+6
\|
*	shiftx2mux: fix select out of bounds	Eddie Hung	2020-02-05	1	-1/+2
\|
*	Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux	Eddie Hung	2020-02-05	2	-2/+0
\|\
\| *	abc9_ops: -write_box is empty, output a dummy box to prevent ABC error	Eddie Hung	2020-01-15	2	-2/+0
\| \|
* \|	Explicitly create separate $mux cells	Eddie Hung	2020-01-21	1	-2/+2
\| \|
* \|	Fix tests -- when Y_WIDTH is non-pow-2	Eddie Hung	2020-01-21	1	-3/+4
\| \|
* \|	Move from +/shiftx2mux.v into +/techmap.v; cleanup	Eddie Hung	2020-01-21	3	-73/+69
\| \|
* \|	New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC	Eddie Hung	2020-01-21	2	-0/+39
\|/
*	Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp	Clifford Wolf	2019-11-11	1	-1/+1
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Makefile: don't assume python is called `python3`	Sean Cross	2019-10-19	1	-2/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
*	Missing (* mul2dsp *) for sliceB	Eddie Hung	2019-09-27	1	-2/+2
\|
*	Stop trying to be too smart by prematurely optimising	Eddie Hung	2019-09-26	1	-34/+6
\|
*	mul2dsp.v slice names	Eddie Hung	2019-09-25	1	-5/+5
\|
*	Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit	Eddie Hung	2019-09-25	1	-3/+1
\|
*	Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"	Eddie Hung	2019-09-25	1	-2/+6
\| \| \| \|	This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1.
*	Revert "No need for $__mul anymore?"	Eddie Hung	2019-09-25	1	-8/+8
\| \| \| \|	This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827.
*	Remove _TECHMAP_CELLTYPE_ check since all $mul	Eddie Hung	2019-09-25	1	-6/+2
\|
*	No need for $__mul anymore?	Eddie Hung	2019-09-25	1	-8/+8
\|
*	Fix signedness bug	Eddie Hung	2019-09-20	1	-2/+2
\|
*	Be sensitive to signedness	Eddie Hung	2019-09-10	1	-20/+21
\|
*	Really get rid of 'opt_expr -fine' by being explicit	Eddie Hung	2019-09-10	1	-6/+33
\|
*	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-09-05	2	-0/+2
\|\
\| *	Use a dummy box file if none specified	Eddie Hung	2019-08-28	2	-0/+2
\| \|
* \|	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	Eddie Hung	2019-08-30	1	-1/+1
\|\ \
\| * \|	Merge branch 'master' into xc7dsp	David Shah	2019-08-30	1	-1/+1
\| \|\\|
\| \| *	Missing newline	Eddie Hung	2019-08-20	1	-1/+1
\| \| \|
* \| \|	Only swap ports if $mul and not $__mul	Eddie Hung	2019-08-13	1	-1/+1
\| \| \|
* \| \|	Add DSP_A_MAXWIDTH_PARTIAL, refactor	Eddie Hung	2019-08-13	1	-144/+110
\|/ /
* \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-08-12	1	-8/+36
\|\\|
\| *	Reformat so it shows up/looks nice when "help $alu" and "help $alu+"	Eddie Hung	2019-08-09	1	-25/+34
\| \|
\| *	A bit more on where $lcu comes from	Eddie Hung	2019-08-09	1	-0/+2
\| \|
\| *	Add more comments	Eddie Hung	2019-08-09	1	-4/+18
\| \|
\| *	Add a few comments to document $alu and $lcu	Eddie Hung	2019-08-08	1	-9/+12
\| \|