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author | Eddie Hung <eddie@fpgeh.com> | 2020-02-06 08:46:38 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-03 14:28:22 -0700 |
commit | 7b09a20c0cc737c3d108c9e981f5989d2ba1423c (patch) | |
tree | 752bc1a6198aff05ad611174ab387859854bfc2d /techlibs/common | |
parent | 34c9b83854a09bb90e8b880774b58d91d7ed8ae7 (diff) | |
download | yosys-7b09a20c0cc737c3d108c9e981f5989d2ba1423c.tar.gz yosys-7b09a20c0cc737c3d108c9e981f5989d2ba1423c.tar.bz2 yosys-7b09a20c0cc737c3d108c9e981f5989d2ba1423c.zip |
cmp2lcu: fail if `LUT_WIDTH < 2
Diffstat (limited to 'techlibs/common')
-rw-r--r-- | techlibs/common/cmp2lcu.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v index b302d592f..b4fadaaad 100644 --- a/techlibs/common/cmp2lcu.v +++ b/techlibs/common/cmp2lcu.v @@ -19,7 +19,7 @@ output [Y_WIDTH-1:0] Y; parameter _TECHMAP_CELLTYPE_ = ""; generate - if (_TECHMAP_CELLTYPE_ == "") + if (_TECHMAP_CELLTYPE_ == "" || `LUT_WIDTH < 2) wire _TECHMAP_FAIL_ = 1; else if (_TECHMAP_CELLTYPE_ == "$lt") begin // Transform $lt into $gt by swapping A and B |