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* | | | Update README.mdClifford Wolf2019-10-051-1/+1
* | | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fixMiodrag Milanović2019-10-051-0/+1
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| * | | Fixes for MSVC buildMiodrag Milanovic2019-10-041-0/+1
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* | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-3/+13
* | | Fix xilinx_dsp for unsigned extensionsEddie Hung2019-10-041-1/+3
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* | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-6/+40
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| * | Add -select option to aigmapEddie Hung2019-09-301-6/+40
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* | Merge pull request #1429 from YosysHQ/clifford/checkmappedClifford Wolf2019-10-031-27/+55
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| * | Add "check -allow-tbuf"Clifford Wolf2019-10-031-8/+22
| * | Add "check -mapped"Clifford Wolf2019-10-021-21/+35
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* | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
* | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* Update doc for equiv_optEddie Hung2019-09-301-2/+3
* Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-1/+1
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| * Open aig frontend as binary fileMiodrag Milanovic2019-09-291-1/+1
* | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2syncClifford Wolf2019-09-301-0/+2
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| * | equiv_opt to call async2sync when not -multiclock like SymbiYosysEddie Hung2019-09-271-0/+2
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* | Fix $dlatch handling in async2syncClifford Wolf2019-09-301-0/+1
* | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2912-229/+2498
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| * Ooops AREG and BREG to default to -1Eddie Hung2019-09-271-2/+2
| * Update doc with max cascade chain of 20Eddie Hung2019-09-261-2/+4
| * Do not always zero out C (e.g. during cascade breaks)Eddie Hung2019-09-262-7/+3
| * Update docEddie Hung2019-09-261-1/+2
| * Zero out portsEddie Hung2019-09-261-2/+2
| * xilinx_dsp_cascade to also cascade AREG and BREGEddie Hung2019-09-262-454/+172
| * Try recursive pmgen for P cascadeEddie Hung2019-09-261-88/+118
| * CREG to check for \keepEddie Hung2019-09-261-0/+3
| * Remove newlineEddie Hung2019-09-261-1/+0
| * Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)Eddie Hung2019-09-251-1/+5
| * Reject if (* init *) presentEddie Hung2019-09-252-0/+6
| * Rework xilinx_dsp postAdd for new wreduce callEddie Hung2019-09-251-3/+3
| * Fix memory issue since SigSpec& could be invalidatedEddie Hung2019-09-251-6/+10
| * unextend only used in initEddie Hung2019-09-251-2/+1
| * Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-5/+4
| * "abc_padding" attr for blackbox outputs that were padded, remove them laterEddie Hung2019-09-231-3/+16
| * Set [AB]CASCREG to legal valuesEddie Hung2019-09-231-6/+10
| * Comment to explain separating CREG packingEddie Hung2019-09-231-0/+8
| * Separate out CREG packing into new pattern, to avoid conflict with PREGEddie Hung2019-09-234-46/+273
| * Move log_debug("\n") laterEddie Hung2019-09-231-1/+1
| * Move unextend initialisation laterEddie Hung2019-09-231-12/+9
| * Use new port() overload once moreEddie Hung2019-09-231-2/+2
| * Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-231-1/+7
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| * | Use new port/param overload in pmgEddie Hung2019-09-204-22/+22
| * | Output pattern matcher items as log_debug()Eddie Hung2019-09-202-31/+27
| * | OPMODE is port not paramEddie Hung2019-09-201-7/+6
| * | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-201-0/+18
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| * | | Do not run xilinx_dsp_cascadeAB for nowEddie Hung2019-09-201-1/+2
| * | | WIP for xiinx_dsp_cascadeABEddie Hung2019-09-201-3/+499
| * | | Run until convergenceEddie Hung2019-09-201-3/+9
| * | | Cleanup ice40_dsp.pmgEddie Hung2019-09-201-12/+6
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