| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -65/+65 | |
| * | | | | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments | Eddie Hung | 2019-10-08 | 4 | -68/+356 | |
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| | * | | | | Missed this | Eddie Hung | 2019-10-05 | 1 | -3/+4 | |
| | * | | | | Add comment on why we have to match for clock-enable/reset muxes | Eddie Hung | 2019-10-05 | 3 | -3/+11 | |
| | * | | | | Add note on pattern detector | Eddie Hung | 2019-10-05 | 1 | -3/+7 | |
| | * | | | | Add comments for xilinx_dsp_cascade | Eddie Hung | 2019-10-04 | 1 | -12/+100 | |
| | * | | | | Improve comments for xilinx_dsp_CREG | Eddie Hung | 2019-10-04 | 1 | -6/+7 | |
| | * | | | | Fix comment | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| | * | | | | Restore optimisation for sigM.empty() | Eddie Hung | 2019-10-04 | 1 | -1/+4 | |
| | * | | | | Retry on fixing TODOs | Eddie Hung | 2019-10-04 | 2 | -13/+1 | |
| | * | | | | Revert "Fix TODOs" | Eddie Hung | 2019-10-04 | 2 | -0/+20 | |
| | * | | | | More comments, cleanup | Eddie Hung | 2019-10-04 | 2 | -41/+108 | |
| | * | | | | Fix TODOs | Eddie Hung | 2019-10-04 | 2 | -20/+0 | |
| | * | | | | Consistency | Eddie Hung | 2019-10-04 | 1 | -3/+3 | |
| | * | | | | Add comments for xilinx_dsp | Eddie Hung | 2019-10-04 | 3 | -6/+134 | |
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| * | | | | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry | Clifford Wolf | 2019-10-06 | 1 | -0/+4 | |
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| | * | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf | Eddie Hung | 2019-10-05 | 1 | -0/+4 | |
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| * | | | | Update README.md | Clifford Wolf | 2019-10-05 | 1 | -1/+1 | |
| * | | | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fix | Miodrag Milanović | 2019-10-05 | 1 | -0/+1 | |
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| | * | | | Fixes for MSVC build | Miodrag Milanovic | 2019-10-04 | 1 | -0/+1 | |
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| * | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -3/+13 | |
| * | | | Fix xilinx_dsp for unsigned extensions | Eddie Hung | 2019-10-04 | 1 | -1/+3 | |
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| * | | Merge pull request #1422 from YosysHQ/eddie/aigmap_select | Clifford Wolf | 2019-10-03 | 1 | -6/+40 | |
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| | * | | Add -select option to aigmap | Eddie Hung | 2019-09-30 | 1 | -6/+40 | |
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| * | | Merge pull request #1429 from YosysHQ/clifford/checkmapped | Clifford Wolf | 2019-10-03 | 1 | -27/+55 | |
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| | * | | Add "check -allow-tbuf" | Clifford Wolf | 2019-10-03 | 1 | -8/+22 | |
| | * | | Add "check -mapped" | Clifford Wolf | 2019-10-02 | 1 | -21/+35 | |
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| * | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 | |
| * | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 | |
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| * | Update doc for equiv_opt | Eddie Hung | 2019-09-30 | 1 | -2/+3 | |
| * | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 1 | -1/+1 | |
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| | * | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 1 | -1/+1 | |
| * | | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+2 | |
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| | * | | equiv_opt to call async2sync when not -multiclock like SymbiYosys | Eddie Hung | 2019-09-27 | 1 | -0/+2 | |
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| * | | Fix $dlatch handling in async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+1 | |
| * | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 12 | -229/+2498 | |
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| | * | Ooops AREG and BREG to default to -1 | Eddie Hung | 2019-09-27 | 1 | -2/+2 | |
| | * | Update doc with max cascade chain of 20 | Eddie Hung | 2019-09-26 | 1 | -2/+4 | |
| | * | Do not always zero out C (e.g. during cascade breaks) | Eddie Hung | 2019-09-26 | 2 | -7/+3 | |
| | * | Update doc | Eddie Hung | 2019-09-26 | 1 | -1/+2 | |
| | * | Zero out ports | Eddie Hung | 2019-09-26 | 1 | -2/+2 | |
| | * | xilinx_dsp_cascade to also cascade AREG and BREG | Eddie Hung | 2019-09-26 | 2 | -454/+172 | |
| | * | Try recursive pmgen for P cascade | Eddie Hung | 2019-09-26 | 1 | -88/+118 | |
| | * | CREG to check for \keep | Eddie Hung | 2019-09-26 | 1 | -0/+3 | |
| | * | Remove newline | Eddie Hung | 2019-09-26 | 1 | -1/+0 | |
| | * | Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed) | Eddie Hung | 2019-09-25 | 1 | -1/+5 | |
| | * | Reject if (* init *) present | Eddie Hung | 2019-09-25 | 2 | -0/+6 | |
| | * | Rework xilinx_dsp postAdd for new wreduce call | Eddie Hung | 2019-09-25 | 1 | -3/+3 | |
| | * | Fix memory issue since SigSpec& could be invalidated | Eddie Hung | 2019-09-25 | 1 | -6/+10 | |
| | * | unextend only used in init | Eddie Hung | 2019-09-25 | 1 | -2/+1 | |
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index : iCE40/yosys | |
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