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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 09:27:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 09:27:12 -0700 |
| commit | 5c68da4150f8e5367138f2c7187f707b20cc19db (patch) | |
| tree | 5ffecc91ae6827340b3261d91e077215eb9c4157 /passes | |
| parent | b47bb5c8100bf24c7075dc322f201779eda280b7 (diff) | |
| download | yosys-5c68da4150f8e5367138f2c7187f707b20cc19db.tar.gz yosys-5c68da4150f8e5367138f2c7187f707b20cc19db.tar.bz2 yosys-5c68da4150f8e5367138f2c7187f707b20cc19db.zip | |
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/ice40_wrapcarry.pmg | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/pmgen/ice40_wrapcarry.pmg b/passes/pmgen/ice40_wrapcarry.pmg index 9e64c7467..bb59edb0c 100644 --- a/passes/pmgen/ice40_wrapcarry.pmg +++ b/passes/pmgen/ice40_wrapcarry.pmg @@ -9,3 +9,7 @@ match lut index <SigSpec> port(lut, \I1) === port(carry, \I0) index <SigSpec> port(lut, \I2) === port(carry, \I1) endmatch + +code + accept; +endcode |