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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 21:42:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 22:31:04 -0700 |
| commit | 8027ebf05b7538e501b4903cab9c2ce6a23610ff (patch) | |
| tree | 86736806f8ca95f6a417c718735179641f0ae48e /passes | |
| parent | 77d7a5c14a6cf7c16b69338ed91d1b9166dba065 (diff) | |
| download | yosys-8027ebf05b7538e501b4903cab9c2ce6a23610ff.tar.gz yosys-8027ebf05b7538e501b4903cab9c2ce6a23610ff.tar.bz2 yosys-8027ebf05b7538e501b4903cab9c2ce6a23610ff.zip | |
Restore optimisation for sigM.empty()
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index dbc3f7455..77d4850d4 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -100,7 +100,10 @@ code sigA sigB sigC sigD sigM clock sigM.append(P[i]); } log_assert(nusers(P.extract_end(i)) <= 1); - log_assert(!sigM.empty()); + // This sigM could have no users if downstream sinks (e.g. $add) is + // narrower than $mul result, for example + if (sigM.empty()) + reject; } else sigM = P; |