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* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-9/+9
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-1/+3
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-4/+2
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* verilog: significant block scoping improvementsZachary Snow2021-01-311-23/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmapwhitequark2020-08-271-5/+3
|\ | | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap
| * flatten, techmap: don't canonicalize tpl driven bits via sigmap.whitequark2020-08-261-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For connection `assign a = b;`, `sigmap(a)` returns `b`. This is exactly the opposite of the desired canonicalization for driven bits. Consider the following code: module foo(inout a, b); assign a = b; endmodule module bar(output c); foo f(c, 1'b0); endmodule Before this commit, the inout ports would be swapped after flattening (and cause a crash while attempting to drive a constant value). This issue was introduced in 9f772eb9. Fixes #2183.
* | Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-2/+2
|/ | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fixclairexen2020-08-201-1/+22
|\ | | | | techmap.CONSTMAP: Handle outputs before inputs.
| * techmap.CONSTMAP: Handle outputs before inputs.Marcelina Kościelnicka2020-08-051-1/+22
| | | | | | | | Fixes #2321.
* | techmap: Add support for [] wildcards in techmap_celltype.Marcelina Kościelnicka2020-08-021-4/+32
|/ | | | Fixes #1826.
* techmap: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-41/+4
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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+6
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* techmap: don't drop attributes on replaced cells.whitequark2020-06-291-2/+3
| | | | | | This was introduced in 76c4ee4ea5cb6a3dc214f66237af22a1bedda010. Fixes #2204.
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-041-7/+1
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* techmap, flatten: remove dead options.whitequark2020-06-041-225/+168
| | | | | | After splitting the passes, some options can never be activated, and most conditions involving them become dead. Remove them, and also all of the newly dead code.
* flatten: split from techmap.whitequark2020-06-031-93/+0
| | | | | | | Although the two passes started out very similar, they diverged over time and now have little in common. Moreover, `techmap` is extremely complex while `flatten` does not have to be, and this complexity interferes with improving `flatten`.
* techmap: remove dead variable. NFC.whitequark2020-06-031-1/+0
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* techmap: use C++11 default member initializers. NFC.whitequark2020-06-021-16/+6
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* techmap: simplify.whitequark2020-06-021-7/+1
| | | | `rewrite_filename` is already called in `Frontend::extra_args`.
* techmap: use +/techmap.v instead of an ad-hoc code generator.whitequark2020-06-021-3/+1
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* techmap: Replace naughty `const_cast<>()`s.Alberto Gonzalez2020-05-141-2/+4
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* techmap: Replace pseudo-private member usage with the range accessor ↵Alberto Gonzalez2020-05-141-3/+3
| | | | function and some naughty `const_cast<>()`s.
* techmap: sort celltypeMap as it determines techmap orderEddie Hung2020-05-141-1/+5
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* Replace `std::set`s using custom comparators with `pool`.Alberto Gonzalez2020-05-141-4/+4
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-141-11/+12
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* Further clean up `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-5/+6
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Use `emplace()` for more efficient insertion into various `dict`s.Alberto Gonzalez2020-05-141-8/+8
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* Build constant bits directly rather than constructing an object and copying ↵Alberto Gonzalez2020-05-141-2/+5
| | | | its bits.
* Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.Alberto Gonzalez2020-05-141-2/+2
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* Use `emplace()` rather than `insert()`.Alberto Gonzalez2020-05-141-1/+1
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* Clean up pseudo-private member usage and ensure range iteration uses ↵Alberto Gonzalez2020-05-141-17/+17
| | | | references where possible to avoid unnecessary copies.
* Clean up extraneous buffer.Alberto Gonzalez2020-05-141-5/+2
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* Replace `std::map` with `dict` for `unique_bit_id`.Alberto Gonzalez2020-05-141-1/+1
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* Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | `cellbits_to_tplbits`.
* Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | `outbit_to_cell`.
* Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
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* Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
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* Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
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* Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
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* Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵Alberto Gonzalez2020-05-141-4/+4
| | | | `std::map` for `techmap_cache` and `techmap_do_cache`.
* Replace `std::map` with `dict` for `simplemap_mappers`.Alberto Gonzalez2020-05-141-1/+1
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* Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-10/+10
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* Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵Alberto Gonzalez2020-05-141-21/+21
| | | | | | `passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Do not modify design modules while iterating over `modules()`.Alberto Gonzalez2020-05-141-1/+4
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Clean up pseudo-private member usage, superfluous `std::vector` ↵Alberto Gonzalez2020-05-141-76/+70
| | | | instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
* techmap: fix error messageEddie Hung2020-04-141-1/+1
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-40/+40
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-2/+2
|\ | | | | kernel: speedup by using more pass-by-const-ref
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