iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fitting help messages to 80 character width	KrystalDelusion	2022-08-24	1	-2/+2
*	memory_share: fix wrong argidx in extra_args	imhcyx	2022-05-05	1	-1/+1
*	memory_share: Fix up mismatched address widths.	Marcelina Kościelnicka	2022-04-15	1	-0/+14
*	memory_share: Fix SAT-based sharing for wide ports.	Marcelina Kościelnicka	2021-12-20	1	-1/+3
*	memory_share: Add -nosat and -nowiden options.	Marcelina Kościelnicka	2021-08-14	1	-7/+29
*	memory_share: Pass addresses through sigmap_xmux everywhere.	Marcelina Kościelnicka	2021-08-13	1	-20/+25
*	kernel/mem: Introduce transparency masks.	Marcelina Kościelnicka	2021-08-11	1	-4/+7
*	Refactor common parts of SAT-using optimizations into a helper.	Marcelina Kościelnicka	2021-08-09	1	-61/+10
*	memory_share: Don't skip ports with EN wired to input for SAT sharing.	Marcelina Kościelnicka	2021-08-04	1	-3/+1
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	memory_share: Add read port merging.	Marcelina Kościelnicka	2021-05-29	1	-0/+140
*	memory_share: Improve sat-based port sharing.	Marcelina Kościelnicka	2021-05-28	1	-117/+151
*	memory_share: Improve same-address merging, recognize wide write ports.	Marcelina Kościelnicka	2021-05-27	1	-204/+77
*	memory_share: Add wide port support.	Marcelina Kościelnicka	2021-05-25	1	-0/+6
*	memory_share: Use Mem helpers.	Marcelina Kościelnicka	2021-05-23	1	-89/+71
*	memory_share: Split off feedback path finding as a separate pass.	Marcelina Kościelnicka	2021-05-23	1	-241/+6
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
*	Add flooring division operator	Xiretza	2020-05-28	1	-0/+1
*	Add flooring modulo operator	Xiretza	2020-05-28	1	-0/+1
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-69/+69
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-19/+19
*	Merge pull request #1845 from YosysHQ/eddie/kernel_speedup	Eddie Hung	2020-04-02	1	-8/+8
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\| *	kernel: SigSpec use more const& + overloads to prevent implicit SigSpec	Eddie Hung	2020-03-13	1	-8/+8
* \|	memory_share: fix stray brace	Eddie Hung	2020-03-30	1	-1/+0
* \|	Code review fixes	Eddie Hung	2020-03-30	1	-2/+2
* \|	Apply suggestions from code review	Eddie Hung	2020-03-30	1	-4/+1
* \|	kernel: share a single CellTypes within a pass	Eddie Hung	2020-03-18	1	-4/+16
\|/
*	Make liberal use of IdString.in()	Eddie Hung	2019-08-06	1	-3/+3
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Typo fix.	Kaj Tuomi	2016-09-08	1	-1/+1
*	Fixed bug in memory_share for memory ports with different ABITS	Clifford Wolf	2016-08-22	1	-0/+6
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Bugfix and improvements in memory_share	Clifford Wolf	2016-04-21	1	-22/+19
*	Renamed opt_share to opt_merge	Clifford Wolf	2016-03-31	1	-1/+1
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Fixed memory_share for unconditional write with part select to memory	Clifford Wolf	2015-04-22	1	-0/+3
*	Replaced ezDefaultSAT with ezSatPtr	Clifford Wolf	2015-02-21	1	-7/+7
*	Added onehot attribute	Clifford Wolf	2015-02-04	1	-0/+13
*	More dict/pool related changes	Clifford Wolf	2014-12-27	1	-2/+2
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-2/+2
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-3/+2
*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	1	-5/+6
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-53/+53
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-0/+2
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-13/+22