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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-22 14:26:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-22 14:26:33 +0200 |
| commit | cad40fc87449e69a086a627bfb25aa49ae400753 (patch) | |
| tree | 48d127797c67d4af110fa3b0fc937ec2adb96816 /passes/memory/memory_share.cc | |
| parent | 7a33b9892a7a542ca1ac0b503c4368a1721a9afb (diff) | |
| download | yosys-cad40fc87449e69a086a627bfb25aa49ae400753.tar.gz yosys-cad40fc87449e69a086a627bfb25aa49ae400753.tar.bz2 yosys-cad40fc87449e69a086a627bfb25aa49ae400753.zip | |
Fixed bug in memory_share for memory ports with different ABITS
Diffstat (limited to 'passes/memory/memory_share.cc')
| -rw-r--r-- | passes/memory/memory_share.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index f298169de..bcb7433a2 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -619,6 +619,12 @@ struct MemoryShareWorker RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); + if (GetSize(last_addr) < GetSize(this_addr)) + last_addr.extend_u0(GetSize(this_addr)); + else + this_addr.extend_u0(GetSize(last_addr)); + + wr_ports[i]->setParam("\\ABITS", GetSize(this_addr)); wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active)); wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active)); |