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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-30 08:19:56 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-30 08:19:56 -0700 |
| commit | f64d59d824424756794fcb8c1fad4d6a088358d8 (patch) | |
| tree | e97a63f4855dd2b425d166a82929f2721407e707 /passes/memory/memory_share.cc | |
| parent | d40f12252b2a7be2cd1a3b3a0562232e41edfec7 (diff) | |
| download | yosys-f64d59d824424756794fcb8c1fad4d6a088358d8.tar.gz yosys-f64d59d824424756794fcb8c1fad4d6a088358d8.tar.bz2 yosys-f64d59d824424756794fcb8c1fad4d6a088358d8.zip | |
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Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
Diffstat (limited to 'passes/memory/memory_share.cc')
| -rw-r--r-- | passes/memory/memory_share.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 236c3c99c..0111c2309 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -665,9 +665,7 @@ struct MemoryShareWorker // Setup and run // ------------- - MemoryShareWorker(RTLIL::Design *design) : - design(design), modwalker(design) - { + MemoryShareWorker(RTLIL::Design *design) : design(design), modwalker(design) {} } void operator()(RTLIL::Module* module) @@ -764,7 +762,6 @@ struct MemorySharePass : public Pass { void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n"); extra_args(args, 1, design); - MemoryShareWorker msw(design); for (auto module : design->selected_modules()) |