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* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-2/+2
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* memory_share: fix wrong argidx in extra_argsimhcyx2022-05-051-1/+1
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* memory_share: Fix up mismatched address widths.Marcelina Kościelnicka2022-04-151-0/+14
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* memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-201-1/+3
| | | | Fixes #3117.
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-141-7/+29
| | | | This unlocks wide port recognition by default.
* memory_share: Pass addresses through sigmap_xmux everywhere.Marcelina Kościelnicka2021-08-131-20/+25
| | | | This fixes wide port recognition in some cases.
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-111-4/+7
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* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-091-61/+10
| | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
* memory_share: Don't skip ports with EN wired to input for SAT sharing.Marcelina Kościelnicka2021-08-041-3/+1
| | | | Fixes #2912.
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* memory_share: Add read port merging.Marcelina Kościelnicka2021-05-291-0/+140
| | | | | This is mostly meant for wide port recognition, but may also happen to merge some ports with compatible initial/reset values (eg. 0 vs x).
* memory_share: Improve sat-based port sharing.Marcelina Kościelnicka2021-05-281-117/+151
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* memory_share: Improve same-address merging, recognize wide write ports.Marcelina Kościelnicka2021-05-271-204/+77
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* memory_share: Add wide port support.Marcelina Kościelnicka2021-05-251-0/+6
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* memory_share: Use Mem helpers.Marcelina Kościelnicka2021-05-231-89/+71
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* memory_share: Split off feedback path finding as a separate pass.Marcelina Kościelnicka2021-05-231-241/+6
| | | | | memory_share is actually three passes in a trenchcoat. Split off the one that has the least in common with the other two as a separate pass.
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* Add flooring division operatorXiretza2020-05-281-0/+1
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-0/+1
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-69/+69
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* kernel: use more ID::*Eddie Hung2020-04-021-19/+19
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-8/+8
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-8/+8
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* | memory_share: fix stray braceEddie Hung2020-03-301-1/+0
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* | Code review fixesEddie Hung2020-03-301-2/+2
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* | Apply suggestions from code reviewEddie Hung2020-03-301-4/+1
| | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
* | kernel: share a single CellTypes within a passEddie Hung2020-03-181-4/+16
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* Make liberal use of IdString.in()Eddie Hung2019-08-061-3/+3
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Typo fix.Kaj Tuomi2016-09-081-1/+1
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* Fixed bug in memory_share for memory ports with different ABITSClifford Wolf2016-08-221-0/+6
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Bugfix and improvements in memory_shareClifford Wolf2016-04-211-22/+19
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* Renamed opt_share to opt_mergeClifford Wolf2016-03-311-1/+1
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* Fixed memory_share for unconditional write with part select to memoryClifford Wolf2015-04-221-0/+3
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* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-211-7/+7
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* Added onehot attributeClifford Wolf2015-02-041-0/+13
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* More dict/pool related changesClifford Wolf2014-12-271-2/+2
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* namespace YosysClifford Wolf2014-09-271-2/+2
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* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
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* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-011-3/+2
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* Renamed modwalker.h to modtools.hClifford Wolf2014-07-311-5/+6
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-53/+53
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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-0/+2
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-13/+22
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