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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-30 08:35:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-30 08:35:40 -0700 |
| commit | 1d93d1e59f5ce222886b785f0a0a553ceeb39c1c (patch) | |
| tree | c72ae53411b16f8fa00eb96df00cf66ebbbcf0eb /passes/memory/memory_share.cc | |
| parent | 4d897975a8fe76191c39442eb7603723a2b84e1d (diff) | |
| download | yosys-1d93d1e59f5ce222886b785f0a0a553ceeb39c1c.tar.gz yosys-1d93d1e59f5ce222886b785f0a0a553ceeb39c1c.tar.bz2 yosys-1d93d1e59f5ce222886b785f0a0a553ceeb39c1c.zip | |
memory_share: fix stray brace
Diffstat (limited to 'passes/memory/memory_share.cc')
| -rw-r--r-- | passes/memory/memory_share.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 8b9d9a04d..c116fccf4 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -666,7 +666,6 @@ struct MemoryShareWorker // ------------- MemoryShareWorker(RTLIL::Design *design) : design(design), modwalker(design) {} - } void operator()(RTLIL::Module* module) { |