iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-51/+51
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-51/+51
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-4/+2
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-2/+0
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-6/+6
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-6/+6
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-2/+2
*	Improved memory_share log messages	Clifford Wolf	2014-07-19	1	-3/+3
*	More verbose memory_share help message	Clifford Wolf	2014-07-19	1	-0/+17
*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19	1	-0/+180
*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19	1	-4/+12
*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18	1	-10/+236
*	Only create collision detect logic in memory_share if necessary	Clifford Wolf	2014-07-18	1	-4/+47
*	Added memory_share	Clifford Wolf	2014-07-18	1	-0/+263