aboutsummaryrefslogtreecommitdiffstats
path: root/passes/fsm
Commit message (Expand)AuthorAgeFilesLines
* fsm_opt: Fix runtime error for FSMs without a reset stateDavid Shah2019-02-071-1/+2
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-022-6/+6
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-209-18/+18
* Remove some dead code from fsm_mapClifford Wolf2017-08-211-3/+0
* Squelch trailing whitespaceLarry Doolittle2017-04-121-2/+2
* Be more conservative with merging large cells into FSMsClifford Wolf2017-01-261-3/+17
* Add warnings for quickly growing FSM table size in fsm_expandClifford Wolf2017-01-261-0/+10
* Added support for fsm_encoding="user"Clifford Wolf2016-11-021-3/+3
* Added "fsm_expand -full"Clifford Wolf2016-11-022-17/+35
* Bugfix in fsm_map for FSMs without reset stateClifford Wolf2016-10-251-1/+2
* Minor bugfix in FSM reset state detectionClifford Wolf2016-07-121-2/+5
* Further improved fsm_detect output, attempt to detect self-resetting circuitsClifford Wolf2016-07-091-6/+68
* Added printing of some warning messages to fsm_detectClifford Wolf2016-07-091-14/+61
* Added "yosys -D" featureClifford Wolf2016-04-219-9/+9
* Added "int ceil_log2(int)" functionClifford Wolf2016-02-131-1/+1
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-241-1/+1
* Do not detect fsm state registers with init attributeClifford Wolf2015-09-211-0/+2
* Added $logic_not handling to fsm_detectClifford Wolf2015-09-181-0/+2
* Bugfix in fsm_detect for complex muxtreesClifford Wolf2015-08-181-15/+23
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-142-3/+3
* Bugfix in fsm_extractClifford Wolf2015-07-031-3/+16
* Fixed trailing whitespacesClifford Wolf2015-07-0210-33/+33
* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-291-1/+3
* Added onehot attributeClifford Wolf2015-02-041-0/+3
* Added "fsm -encfile"Clifford Wolf2015-01-302-12/+41
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-2/+2
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
* Added log_warning() APIClifford Wolf2014-11-091-1/+1
* Changed from "and" to "&&"William Speirs2014-10-151-1/+1
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-112-4/+4
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-105-20/+20
* namespace YosysClifford Wolf2014-09-2710-3/+47
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-301-1/+6
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-301-0/+10
* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-301-20/+75
* Added module->uniquify()Clifford Wolf2014-08-161-5/+1
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-4/+4
* RIP $safe_pmuxClifford Wolf2014-08-143-3/+3
* Some improvements in FSM mapping and recodingClifford Wolf2014-08-142-8/+16
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-101-1/+21
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-092-50/+101
* Another fsm_extract bugfixClifford Wolf2014-08-081-0/+4
* Fixed "fsm -export"Clifford Wolf2014-08-082-6/+5
* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-081-8/+25
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-023-4/+4
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-316-84/+84
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-2/+2
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 16:08:57 +0000