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| author | whitequark <whitequark@whitequark.org> | 2018-12-07 19:14:07 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-01-02 13:12:17 +0000 |
| commit | efa278e232d20ea080743801bd91d55ec62955cf (patch) | |
| tree | 61971fdccdc1bb24169d78d0193eccc957232536 /passes/fsm | |
| parent | 4b9f619349e6b7452739631635ab3b5a4d94b522 (diff) | |
| download | yosys-efa278e232d20ea080743801bd91d55ec62955cf.tar.gz yosys-efa278e232d20ea080743801bd91d55ec62955cf.tar.bz2 yosys-efa278e232d20ea080743801bd91d55ec62955cf.zip | |
Fix typographical and grammatical errors and inconsistencies.
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 8 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index fc504e98c..5ae991b28 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -196,13 +196,13 @@ static void detect_fsm(RTLIL::Wire *wire) vector<string> warnings; if (is_module_port) - warnings.push_back("Forcing fsm recoding on module port might result in larger circuit.\n"); + warnings.push_back("Forcing FSM recoding on module port might result in larger circuit.\n"); if (!looks_like_good_state_reg) - warnings.push_back("Users of state reg look like fsm recoding might result in larger circuit.\n"); + warnings.push_back("Users of state reg look like FSM recoding might result in larger circuit.\n"); if (has_init_attr) - warnings.push_back("Init value on fsm state registers are ignored. Possible simulation-synthesis mismatch!"); + warnings.push_back("Initialization value on FSM state register is ignored. Possible simulation-synthesis mismatch!\n"); if (!looks_like_state_reg) warnings.push_back("Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!\n"); @@ -236,7 +236,7 @@ static void detect_fsm(RTLIL::Wire *wire) log(" Users of register don't seem to benefit from recoding.\n"); if (has_init_attr) - log(" Register has an initialization value."); + log(" Register has an initialization value.\n"); if (is_self_resetting) log(" Circuit seems to be self-resetting.\n"); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 67551f673..6095eaf30 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -178,7 +178,7 @@ undef_bit_in_next_state: log_state_in = fsm_data.state_table.at(state_in); if (states.count(ce.values_map(ce.assign_map(dff_in)).as_const()) == 0) { - log(" transition: %10s %s -> INVALID_STATE(%s) %s <ignored invalid transistion!>%s\n", + log(" transition: %10s %s -> INVALID_STATE(%s) %s <ignored invalid transition!>%s\n", log_signal(log_state_in), log_signal(tr.ctrl_in), log_signal(ce.values_map(ce.assign_map(dff_in))), log_signal(tr.ctrl_out), undef_bit_in_next_state_mode ? " SHORTENED" : ""); @@ -194,7 +194,7 @@ undef_bit_in_next_state: log_signal(log_state_in), log_signal(tr.ctrl_in), log_signal(fsm_data.state_table[tr.state_out]), log_signal(tr.ctrl_out)); } else { - log(" transition: %10s %s -> %10s %s <ignored undef transistion!>\n", + log(" transition: %10s %s -> %10s %s <ignored undef transition!>\n", log_signal(log_state_in), log_signal(tr.ctrl_in), log_signal(fsm_data.state_table[tr.state_out]), log_signal(tr.ctrl_out)); } |