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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-24 22:56:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-24 22:56:40 +0200 |
| commit | 7f110e7018d35f29cf6a5d3031400a8044c8d32d (patch) | |
| tree | 9c65e6929e43faec716efab17b37bd53f9afa4b3 /passes/fsm | |
| parent | 6af80769678f260aa4aeaf3b12b54dfdc15fa5dd (diff) | |
| download | yosys-7f110e7018d35f29cf6a5d3031400a8044c8d32d.tar.gz yosys-7f110e7018d35f29cf6a5d3031400a8044c8d32d.tar.bz2 yosys-7f110e7018d35f29cf6a5d3031400a8044c8d32d.zip | |
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_opt.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 7322368cd..a7cc95ffa 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -78,7 +78,7 @@ struct FsmOpt bool signal_is_unused(RTLIL::SigSpec sig) { - RTLIL::SigBit bit = sig.to_single_sigbit(); + RTLIL::SigBit bit = sig.as_bit(); if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0) return false; |