iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Remove some dead code from fsm_map	Clifford Wolf	2017-08-21	1	-3/+0
*	Squelch trailing whitespace	Larry Doolittle	2017-04-12	1	-2/+2
*	Be more conservative with merging large cells into FSMs	Clifford Wolf	2017-01-26	1	-3/+17
*	Add warnings for quickly growing FSM table size in fsm_expand	Clifford Wolf	2017-01-26	1	-0/+10
*	Added support for fsm_encoding="user"	Clifford Wolf	2016-11-02	1	-3/+3
*	Added "fsm_expand -full"	Clifford Wolf	2016-11-02	2	-17/+35
*	Bugfix in fsm_map for FSMs without reset state	Clifford Wolf	2016-10-25	1	-1/+2
*	Minor bugfix in FSM reset state detection	Clifford Wolf	2016-07-12	1	-2/+5
*	Further improved fsm_detect output, attempt to detect self-resetting circuits	Clifford Wolf	2016-07-09	1	-6/+68
*	Added printing of some warning messages to fsm_detect	Clifford Wolf	2016-07-09	1	-14/+61
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	9	-9/+9
*	Added "int ceil_log2(int)" function	Clifford Wolf	2016-02-13	1	-1/+1
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-1/+1
*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24	1	-1/+1
*	Do not detect fsm state registers with init attribute	Clifford Wolf	2015-09-21	1	-0/+2
*	Added $logic_not handling to fsm_detect	Clifford Wolf	2015-09-18	1	-0/+2
*	Bugfix in fsm_detect for complex muxtrees	Clifford Wolf	2015-08-18	1	-15/+23
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	2	-3/+3
*	Bugfix in fsm_extract	Clifford Wolf	2015-07-03	1	-3/+16
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	10	-33/+33
*	Added $eq/$neq -> $logic_not/$reduce_bool optimization	Clifford Wolf	2015-04-29	1	-1/+3
*	Added onehot attribute	Clifford Wolf	2015-02-04	1	-0/+3
*	Added "fsm -encfile"	Clifford Wolf	2015-01-30	2	-12/+41
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-2/+2
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-1/+1
*	Changed from "and" to "&&"	William Speirs	2014-10-15	1	-1/+1
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11	2	-4/+4
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	5	-20/+20
*	namespace Yosys	Clifford Wolf	2014-09-27	10	-3/+47
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
*	Don't change existing binary FSM encoding if it is already optimal	Clifford Wolf	2014-08-30	1	-1/+6
*	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	Clifford Wolf	2014-08-30	1	-0/+10
*	Improved handling of $pmux cells in fsm_extract	Clifford Wolf	2014-08-30	1	-20/+75
*	Added module->uniquify()	Clifford Wolf	2014-08-16	1	-5/+1
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-4/+4
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	3	-3/+3
*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14	2	-8/+16
*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10	1	-1/+21
*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09	2	-50/+101
*	Another fsm_extract bugfix	Clifford Wolf	2014-08-08	1	-0/+4
*	Fixed "fsm -export"	Clifford Wolf	2014-08-08	2	-6/+5
*	Fixed fsm_extract for wreduced muxes	Clifford Wolf	2014-08-08	1	-8/+25
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	3	-4/+4
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	6	-84/+84
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-2/+2
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	2	-4/+4
*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27	1	-4/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	8	-8/+8