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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-2/+2
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
* Added log_warning() APIClifford Wolf2014-11-091-1/+1
* Changed from "and" to "&&"William Speirs2014-10-151-1/+1
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-112-4/+4
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-105-20/+20
* namespace YosysClifford Wolf2014-09-2710-3/+47
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-301-1/+6
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-301-0/+10
* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-301-20/+75
* Added module->uniquify()Clifford Wolf2014-08-161-5/+1
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-4/+4
* RIP $safe_pmuxClifford Wolf2014-08-143-3/+3
* Some improvements in FSM mapping and recodingClifford Wolf2014-08-142-8/+16
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-101-1/+21
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-092-50/+101
* Another fsm_extract bugfixClifford Wolf2014-08-081-0/+4
* Fixed "fsm -export"Clifford Wolf2014-08-082-6/+5
* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-081-8/+25
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-023-4/+4
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-316-84/+84
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-2/+2
* Using log_assert() instead of assert()Clifford Wolf2014-07-282-4/+4
* Added log_cmd_error_expectionClifford Wolf2014-07-271-4/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-278-8/+8
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-278-13/+13
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-272-5/+5
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-262-19/+6
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-263-10/+10
* Manual fixes for new cell connections APIClifford Wolf2014-07-263-9/+17
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-266-94/+94
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-266-94/+94
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-253-60/+19
* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-231-4/+4
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-5/+0
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-8/+8
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-8/+8
* SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commandsClifford Wolf2014-07-223-38/+19
* fixed memory leak in fsm_optClifford Wolf2014-07-221-1/+3
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-2/+2
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-226-58/+58
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-226-58/+58
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-111-1/+2
* Fixes in fsm detect/extract for better detection of non-fsm circuitsClifford Wolf2013-12-062-4/+4
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-046-12/+12
* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-301-4/+15
* Some fixes to improve determinismClifford Wolf2013-08-092-28/+31
* Sort ctrl signals in fsm_extractClifford Wolf2013-08-081-0/+3