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* Support custom PROGRAM_PREFIXMiodrag Milanovic2020-04-102-1/+11
* Merge pull request #1562 from whitequark/write_cxxrtlwhitequark2020-04-102-0/+5
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| * write_cxxrtl: new backend.whitequark2020-04-092-0/+5
* | Merge pull request #1858 from YosysHQ/eddie/fix1856Eddie Hung2020-04-093-3/+3
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| * | kernel: include "kernel/constids.inc" instead of "constids.inc"Eddie Hung2020-04-093-3/+3
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* / [NFCI] Deduplicate builtin FF cell types listMarcelina Kościelnicka2020-04-092-0/+49
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-0210-679/+822
* kernel: IdString::in(const IdString &) as per @TjoppenEddie Hung2020-04-021-1/+1
* kernel: fix formatting (thanks @boqwxp)Eddie Hung2020-04-021-6/+4
* kernel: use C++11 fold hack to prevent recursionEddie Hung2020-04-021-3/+8
* Revert "kernel: IdString:in() to use perfect forwarding"Eddie Hung2020-04-021-2/+2
* kernel: separate IdString::put_reference() out to help inliningEddie Hung2020-04-021-1/+4
* kernel: IdString:in() to use perfect forwardingEddie Hung2020-04-021-2/+2
* kernel: Use constids.inc for global/constant IdStringsEddie Hung2020-04-024-17/+37
* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-024-505/+477
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| * kernel: pass-by-value into Design::scratchpad_set_string() tooEddie Hung2020-03-272-3/+3
| * kernel: const Wire* overload -> Wire* !!!Eddie Hung2020-03-261-1/+1
| * kernel: Cell::set{Port,Param}() to pass by value, but use std::moveEddie Hung2020-03-262-7/+7
| * kernel: SigSpec copies to not trigger pack()Eddie Hung2020-03-182-34/+5
| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-183-361/+355
| * kernel: speedupEddie Hung2020-03-181-30/+23
| * kernel: use const reference for SigSet tooEddie Hung2020-03-171-18/+18
| * kernel: fix DeleteWireWorkerEddie Hung2020-03-171-9/+4
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-132-38/+52
| * kernel: optimise Module::remove(const pool<RTLIL::Wire*>()Eddie Hung2020-03-122-10/+9
| * kernel: SigPool to use const& + overloads to prevent implicit SigSpecEddie Hung2020-03-121-19/+25
* | Merge pull request #1828 from YosysHQ/eddie/celltypes_speedupEddie Hung2020-04-011-10/+3
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| * | kernel: share a single CellTypes within a passEddie Hung2020-03-181-10/+3
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* | Clean up pseudo-private member usage in `kernel/yosys.cc`.Alberto Gonzalez2020-04-011-14/+13
* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-272-1/+6
* | Update CopyrightClaire Wolf2020-03-161-1/+1
* | License: bump year and add titleWaldir Pimenta2020-03-141-1/+1
* | exclude clang from checkingMiodrag Milanovic2020-03-131-1/+1
* | Add YS_ prefix to macros, add explanation and apply to older version as wellMiodrag Milanovic2020-03-133-20/+23
* | Use boost xpressive for gcc 4.8Miodrag Milanovic2020-03-133-23/+29
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* Fix compilation for emccjiegec2020-03-112-1/+4
* Add ScriptPass::run_nocheck and use for abc9David Shah2020-03-092-0/+13
* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+0
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| * Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-231-2/+0
* | Small fixesEddie Hung2020-02-271-2/+2
* | Fixes for older compilersEddie Hung2020-02-271-1/+8
* | Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-271-4/+5
* | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-271-9/+19
* | Fix spacingEddie Hung2020-02-271-50/+50
* | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-3/+4
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-1/+4
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-18/+2
* | abc9_ops: add and use new TimingInfo structEddie Hung2020-02-271-0/+173
* | Merge pull request #1705 from YosysHQ/logger_passMiodrag Milanović2020-02-263-2/+100
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| * Remove duplicate warning detectionMiodrag Milanovic2020-02-231-0/+6