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author | Eddie Hung <eddie@fpgeh.com> | 2020-02-18 08:41:48 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
commit | 9dcf204dece518a48192a90ea962a9d630283e11 (patch) | |
tree | 0903d1fda546051d2c2e8ac7f8af41334ca5d7a4 /kernel | |
parent | 7c3b4b80ea62c53e3f4bd6d91dcf02ef09c40da7 (diff) | |
download | yosys-9dcf204dece518a48192a90ea962a9d630283e11.tar.gz yosys-9dcf204dece518a48192a90ea962a9d630283e11.tar.bz2 yosys-9dcf204dece518a48192a90ea962a9d630283e11.zip |
TimingInfo: index by (port_name,offset)
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/timinginfo.h | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index e2af4d51a..8d0904175 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -25,17 +25,27 @@ YOSYS_NAMESPACE_BEGIN -typedef std::pair<RTLIL::SigBit,RTLIL::SigBit> BitBit; - -struct ModuleTiming -{ - RTLIL::IdString type; - dict<BitBit, int> comb; - dict<RTLIL::SigBit, int> arrival, required; -}; - struct TimingInfo { + struct NameBit + { + RTLIL::IdString name; + int offset; + NameBit() {} + NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {} + bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; } + bool operator!=(const NameBit& nb) const { return !operator==(nb); } + unsigned int hash() const { return mkhash_add(name.hash(), offset); } + }; + typedef std::pair<NameBit,NameBit> BitBit; + + struct ModuleTiming + { + RTLIL::IdString type; + dict<BitBit, int> comb; + dict<NameBit, int> arrival, required; + }; + dict<RTLIL::IdString, ModuleTiming> data; TimingInfo() |